Hardware utilization-aware thread management in multithreaded computer systems

#The present invention relates generally to computer systems and, more particularly, but not exclusively to managing threads in multithreaded computer systems.

#Though processors on computer systems operate at high speeds, they may perform inefficiently due to delays, such as those that occur while waiting to access memory. Fast cache memory is one way to reduce these delays, but a cache miss, which occurs when a desired block of memory is not in the cache and must be retrieved from external caches or memory, causes CPU idling, resulting in execution delay.

#One technique for reducing processor idling is the use of hardware multithreading to achieve processor execution during otherwise idle cycles. In a multithreaded processor, two or more threads of execution may concurrently exist on the processor. Hardware multithreading may employ the replication of registers for each thread in order to minimize the overhead of switching between threads. This technique is called “vertical multithreading.”

#Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified.

#For a better understanding of the present invention, reference will be made to the following Detailed Description, which is to be read in association with the accompanying drawings, wherein:

#FIG. 1 is a block diagram illustrating one embodiment of a multiple core, multithreaded processor;

#The present invention now will be described more fully hereinafter with reference to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific exemplary embodiments by which the invention may be practiced. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Among other things, the present invention may be embodied as methods or devices. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. The following detailed description is, therefore, not to be taken in a limiting sense.

#Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The phrase “in one embodiment” as used herein does not necessarily refer to the same embodiment, though it may. Furthermore, the phrase “in another embodiment” as used herein does not necessarily refer to a different embodiment, although it may. Thus, as described below, various embodiments of the invention may be readily combined, without departing from the scope or spirit of the invention.

#In addition, as used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. In addition, throughout the specification, the meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”