Clock jitter suppression method and computer-readable storage medium
AssigneeFujitsu Limited
InventorKotaro Kishi
Life of this patent
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Abstract
A value held in storage elements coupled to a clock buffer and variably set with a threshold voltage is read out in a state where an analyzing target circuit within an IC operates. An analyzing process specifies an impact of noise in a power supply or ground voltage of the clock buffer and a location where the impact is large, based on the threshold voltage and position information of the storage element from which the read out value has an inverted relationship to the set logic value and each storage element that is a read target. A constraint condition for placement of constituent elements of the IC and routing therein is created from results of the analyzing process, and a re-placement or re-routing process re-places or re-routes the constraint condition to reduce the noise.
Claims11
A clock jitter suppression method for suppressing clock jitter in a semiconductor integrated circuit having a clock buffer configured to receive a clock, comprising:
- setting an arbitrary logic value to storage elements that are coupled to the clock buffer;
- variably setting a threshold voltage of the storage elements;
- reading a value held in the storage elements in a state where an analyzing target circuit within the semiconductor integrated circuit operates;
- performing an analyzing process to specify an extent of an effect of noise in a power supply voltage or a ground voltage of the clock buffer and to specify a location where the effect of the noise is greater than or equal to a predetermined amount within the semiconductor integrated circuit, based on the threshold voltage and position information of the storage element from which the read out value has an inverted relationship to the set arbitrary logic value and each storage element that is a read target;
- performing a constraint condition creating process to create a constraint condition for placement of constituent elements of the semiconductor integrated circuit and routing within the semiconductor integrated circuit based on results of the analyzing process;
- and
- performing one of a re-placement process to modify and re-place the placement of the constraint condition and a re-routing process to modify and re-route the routing of the constraint condition, in order to reduce the noise.
A non-transitory computer-readable storage medium that stores a program which, when executed by a computer, causes the computer to perform a process of suppressing clock jitter in a semiconductor integrated circuit having a clock buffer configured to receive a clock, said process comprising:
- a setting procedure causing the computer to set an arbitrary logic value to storage elements that are coupled to the clock buffer;
- a variably setting procedure causing the computer to variably set a threshold voltage of the storage elements;
- a reading procedure causing the computer to read a value held in the storage elements in a state where an analyzing target circuit within the semiconductor integrated circuit operates;
- an analyzing procedure causing the computer to perform an analyzing process to specify an extent of an effect of noise in a power supply voltage or a ground voltage of the clock buffer and to specify a location where the effect of the noise is greater than or equal to a predetermined amount within the semiconductor integrated circuit, based on the threshold voltage and position information of the storage element from which the read out value has an inverted relationship to the set arbitrary logic value and each storage element that is a read target;
- a creating procedure causing the computer to perform a constraint condition creating process to create a constraint condition for placement of constituent elements of the semiconductor integrated circuit and routing within the semiconductor integrated circuit based on results of the analyzing process;
- and
- a performing procedure causing the computer to perform one of a re-placement process to modify and re-place the placement of the constraint condition and a re-routing process to modify and re-route the routing of the constraint condition, in order to reduce the noise.
Dependencies are inferred from the claim text.