Method of product performance improvement by selective feature sizing of semiconductor devices

A design and simulation system, comprising:

• a processor adapted to obtain performance improvement within an integrated circuit by selectively altering device features within the integrated circuit by performing functions including,
• collecting performance metrics of the devices contained within the integrated circuit, each performance metric being one of a leakage current measurement or a threshold voltage measurement;
• wherein each device has a respective individual performance metric value;
• categorizing each device into one bin of a plurality of bins in response to the collected performance metrics;
• wherein the categorizing includes categorizing all of the devices that have respective individual performance metric values that are within a range of performance metric values into a respective one of the plurality of bins, and the range of the respective individual performance metric values of the devices categorized into each of the plurality of bins does not overlap the range of the respective individual performance metric values of the devices categorized into any other of the plurality of bins;
• tagging each bin with a respective sizing adjustment;
• wherein the plurality of bins includes at least two bins that are tagged with different respective sizing adjustments that are not equal to zero;
• selectively altering feature sizes of each device categorized in each bin in accordance with the tagged sizing adjustment for each bin;
• and
• wherein the feature sizes are selectively altered by modifying one or more mask layers that define the feature sizes of devices categorized within the bins that are tagged with non-zero sizing adjustments.

A method of obtaining performance improvement within an integrated circuit by selective feature sizing of semiconductor devices contained within the integrated circuit, the method comprising:

• implementing a first integrated circuit;
• collecting performance metrics of the devices contained within the integrated circuit, each performance metric being one of a leakage current measurement or a threshold voltage measurement;
• wherein each semiconductor device has a respective individual performance metric value;
• categorizing each semiconductor device contained within the first integrated circuit into one bin of a plurality of bins, wherein each bin is tagged with a respective sizing adjustment that is necessary to bring each semiconductor device categorized within the bin into conformance with an acceptable performance level, and the plurality of bins includes at least two bins that are tagged with different respective sizing adjustments that are not equal to zero;
• and
• wherein the categorizing includes categorizing all of the semiconductor devices that have respective performance individual metric values that are within a range of performance metric values into a respective one of the plurality of bins, and the range of the respective individual performance metric values of the devices categorized into each of the plurality of bins does not overlap the range of the respective individual performance metric values of the devices categorized into any other of the plurality of bins:
• selectively altering mask layers that define feature sizes of each semiconductor device categorized in each of the plurality of bins in accordance with the tagged sizing adjustment of each bin.