I/O cell architecture

#The disclosed systems and methods relate to integrated circuits. More specifically, the disclosed systems and methods relate to the layout and architecture of an input/output (“I/O”) cell of an integrated circuit (“IC”).

#I/O cells are provided on IC chips to enable signals and power to be routed between one IC chip and another IC chip or device. Conventionally, each I/O cell is provided with a certain unique purpose such as providing a specific function or power level, e.g., ground or operating voltage.

#As integrated circuits continue to decrease in size, the bonding pitch for each I/O cell is also decreased. The decrease in bonding pitch for I/O cells results in the internal interconnects of the I/O cells being comparatively lengthened, which increases the influence of the interconnect capacitance. Additionally, the decrease in bonding pitch results in a greater potential for electromigration due to thinner interconnects distributing the same amount of power to and from the IC chip.

#FIG. 1 is a plan view of an integrated circuit and a substrate having corresponding I/O cell and bonding pad locations.

#FIG. 2A is a plan view of one example of an integrated circuit including a plurality of I/O cells.

#FIG. 2B is a schematic illustration of one example of an I/O cell of the integrated circuit illustrated in FIG. 2A.

#FIG. 1 illustrates an integrated circuit (“IC”) 100 including a plurality of input/output (“I/O”) cells 102 disposed around the periphery of active area 104. Each I/O cell 102 includes an I/O pad 104 for bonding or otherwise coupling to another IC, device, or substrate 108 having a plurality of corresponding bonding pads 110 as will be understood by one skilled in the art. The pitch dimensions for the I/O bonding pads 104 (the pad-to-pad repeat distance on a chip) is typically standardized across the industry by the International Technology Roadmap for Semiconductors (“ITRS”) for each processing technology. The pitch dimension for the I/O bonding pads dictates the height of the I/O cell (referred to herein as “I/O cell pitch”).

#FIG. 2A illustrates one example of an IC 200 including a plurality of I/O cells 202 having an improved architecture and being disposed around the periphery of the active area 204 of IC 200. I/O cells 202 include circuitry 208, 210, and 212 for providing multiple functionalities within a single I/O cell 202 (e.g., data transfer, ground level, operating voltage, or the like). By grouping a plurality of functions into a single I/O cell 202, the full area and metal resources of the I/O cell may be utilized and shared across all of the function-specific circuitry of the I/O cell.

#For example, FIG. 2B illustrates one example of an improved I/O cell 202 that includes a plurality of bonding pads 206-1, 206-2, and 206-3 (collectively referred to as “bonding pads 206”) and circuitry for supplying the ground and operating voltages 208 as well as data transport 210, 212 to IC 204. I/O cell 202 may include circuitry for providing other functionality such as an electrostatic discharge (“ESD”) trigger or clamp circuit as will be understood by one skilled in the art.