US 8,302,058 B1 · Reducing simultaneous switching noise in an integrated circuit design during placement

Abstract

Methods, computer programs, and Integrated Circuits (IC) for minimizing Simultaneous Switching Noise (SSN) in the design of an IC are presented. In one embodiment, the method includes moving a candidate pin of the IC in an initial input/output (I/O) layout to create a candidate I/O layout. Further, in one operation the method calculates a first performance cost for the initial I/O layout and a second performance cost for the candidate I/O layout. The first and the second performance costs are based on an SSN cost for the initial layout and on an SSN cost for the candidate layout respectively. The method selects the layout to design the IC that has the lowest performance cost. The method operations are performed during the placement phase of an IC Computer Aided Design (CAD) tool.

Claims18

Dependent claims

A method to reduce Simultaneous Switching Noise (SSN) in an Integrated Circuit (IC) design, the method comprising:

moving a candidate pin of the IC design in an initial input/output (I/O) layout to create a candidate I/O layout;
calculating a first performance cost for the initial I/O layout and a second performance cost for the candidate I/O layout, wherein the first and second performance costs are based on an SSN cost for the initial I/O layout and on an SSN cost for the candidate I/O layout respectively,
wherein calculating the SSN cost for the candidate I/O layout includes,
prior to said moving, establishing a bounding box which includes pins in a first region centered around the candidate pin;
subsequent to said moving, establishing a bounding box which includes pins in a second region centered around the candidate pin;
recalculating the pin cost functions for the pins in the bounding box;
and
selecting a layout for the IC design that has a lower performance cost, wherein at least one method operation is executed through a processor.

5 more elements

A computer program embedded in a computer-readable storage medium, when executed by one or more processors, for reducing Simultaneous Switching Noise (SSN) in Integrated Circuit (IC) design, the computer program comprising:

program instructions for moving a candidate pin of the IC in an initial input/output (I/O) layout to create a candidate I/O layout;
program instructions for calculating a first SSN cost for the initial I/O layout and a second SSN cost for the candidate I/O layout, the program instruction for calculating further comprising:
program instructions for recalculating the pin cost function for pins within a bounding box;
and
program instructions for using the pin cost functions obtained during the first SSN cost calculation for pins outside the bounding box;
and
program instructions for selecting a layout to design the IC with a lowest SSN cost;
wherein the computer program performs placement operations in an IC Computer Aided Design (CAD) tool.

5 more elements

Dependencies are inferred from the claim text.

Reducing simultaneous switching noise in an integrated circuit design during placement

Life of this patent

Reducing simultaneous switching noise in an integrated circuit design during placement

Life of this patent

Abstract

Claims18