System and method for extracting parasitic elements
AssigneeRenesas Electronics Corporation
InventorHiromitsu Tsunoda
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AssigneeRenesas Electronics Corporation
InventorHiromitsu Tsunoda
Estimating the term…
A parasitic element extracting system includes: a classifying section configured to classify each of interconnection layers of a layout structure of a semiconductor device into one of an upper interconnection layer and an lower interconnection layer based on a predetermined criterion; and a marker producing section configured to generate a marker to indicate a via-contact connecting the upper interconnection layers and the lower interconnection layers. An upper layer parasitic element list producing section is configured to generate an upper layer parasitic element list by extracting parasitic elements in the upper interconnection layers based on a first criterion, and a lower layer parasitic element list producing section is configured to generate a lower layer parasitic element list by extracting parasitic elements in the lower interconnection layers based on a second criterion which is different from the first criterion. A parasitic element list producing section is configured to generate a parasitic element list of the layout by combining the upper layer parasitic element list and the lower layer parasitic element list by using the markers.
A parasitic element extracting system comprising:
An extracting method of parasitic elements, comprising:
A non-transitory computer-readable tangible storage medium in which a computer-executable program code is stored to realize an extracting method of parasitic elements, wherein said extracting method comprises:
Dependencies are inferred from the claim text.