Automatic debug apparatus and method for automatic debug of an integrated circuit design

A computerized method of characterizing a design under verification (DUV) by a set of computers on a computer farm, the method comprising:

• executing in a Verification environment (VE) a set of verification tests on a DUV to stimulate the DUV to collect test results from the DUV;
• collecting a set of failure data for the test results;
• generating sets of common failures based on clusters of failure features of interest in the set of failure data;
• generating a set of simplified tests from the set of verification tests based on the sets of common failures by removing a portion of the set of verification tests, wherein the simplified tests includes failing tests from the set of verification tests;
• executing in the VE the set of simplified tests on the DUV to collect test results from the DUV;
• generating a set of hints from the test results from the execution of the set of simplified tests;
• wherein the hints indicate a potential failure mode or a potential root cause failure of the DUV for the test results for the simplified set of tests;
• generating a set of debug data from trace information collected during the execution of the set of verification tests;
• and
• transferring the set of hints and the set of debug data to a user computer for storage, display, and use in an interactive debug session of the DUV.

A non-transitory computer readable storage medium containing program instructions that, when executed by a controller within a computer, cause the controller to execute a method for characterizing a design under valuation (DUV) by a set of computers on a computer farm, the method comprising:

• executing in a verification environment (VE) a set of verification tests on a DUV to stimulate the DUV to collect test results from the DUV;
• collecting a set of failure data for the test results;
• generating sets of common failures by clustering the failure data;
• generating a set of simplified tests from the set of verification tests based on the sets of common failures by removing a portion of the set of verification tests, wherein the simplified tests includes failing tests from the set of verification tests;
• executing in the VE the set of simplified tests on the DUV to collect a test results from the DUV;
• generating a set of hints from the test results from the execution of the set of simplified tests;
• wherein the hints indicate a potential failure mode or a potential root cause failure of the DUV for the test results for the simplified set of tests;
• generating a set of debug data from trace information collected during the execution of the set of verification tests;
• and
• transferring the set of hints and the set of debug data to a user computer for storage, display, and use in an interactive debug session of the DUV.

A computer system for characterizing a design under valuation (DUV) comprising a set of computers on a computer farm, wherein each computer includes a processor and a memory configured to store computer code, which is configured to be executed by the processor, wherein each processor of each computer is configured to execute a portion of the method, which includes the steps of:

• executing in a verification environment (VE) a set of verification tests on a DUV to stimulate the DUV to collect test results from the DUV;
• collecting a set of failure data for the test results;
• generating sets of common failures based on clusters of failure features of interest in the set of failure data;
• generating a set of simplified tests by removing a portion of the set of verification tests, wherein the set of simplified tests executing the set of simplified test;
• generating a set of hints from the set of simplified tests, wherein the hints indicate a potential failure mode or a potential root cause failure of the DUV for the test results for the set of simplified tests;
• generating a set of debug data from the set of simplified tests;
• and
• transferring the set of hints and the set of debug data to a user computer for storage, display, and use in an interactive debug session of the DUV.