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AssigneeTexas Instruments Incorporated
InventorsDennis Darcy Buss, Alice Wang, Gordon Gammie, Jle Gu, Rahul Jagdish Rithe, Satyendra R. P. Raju Datla, Sharon Hsiao-Wei Chou
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A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.
A method for simulating timing path delay of an integrated circuit design using a computer aided design (CAD) tool executed by a processor, the method comprising:
A method for simulating timing path delay of an integrated circuit design using a computer aided design (CAD) tool executed by a processor, the method comprising:
A method for simulating timing path delay of an integrated circuit design using a computer aided design (CAD) tool executed by a processor, the method comprising:
A method for simulating timing path delay of an integrated circuit design using a computer aided design (CAD) tool executed by a processor, the method comprising:
A method for simulating timing path delay of an integrated circuit design using a computer aided design (CAD) tool executed by a processor, the method comprising:
A method for simulating timing path delay of an integrated circuit design using a computer aided design (CAD) tool executed by a processor, the method comprising:
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About 3 years 10 months of term left · ends 28 Aug 2030 (estimated)
This invention relates to simulation of integrated circuits, and, in particular, to simulation of low voltage circuits in which the Probability Density Function (PDF) of the stochastic gate delay is non-Gaussian
A timing Path (TP) is a serial connection of logic elements or cells. An input is made to the TP, and the computation is made as the signal propagates through the TP. The TP delay is of interest in designing a chip: This determines the speed of the chip. The TP delay is the sum of cell delays. Traditional static timing analysis (STA) is, and has been, the method that virtually every digital design team uses to achieve timing signoff. In STA, a timing model is required for every cell in the design, or at least for the signal paths that are analyzed. The analyzer uses those timing models to calculate delays for all cells in a given path. Those delays, in turn, are summed to determine total path delays.
Statistical static timing analysis (SSTA) was developed to account for process variation by using probability distributions. In current implementations, the parameters that vary are typically gate length, gate width, flat-band voltage, oxide thickness and channel doping. These parameters are assumed to vary from one chip to another (global variation), but, within a die, they are assumed to be constant.
Particular embodiments in accordance with the invention will now be described, by way of example only, and with reference to the accompanying drawings:
FIG. 1 is a plot illustrating Gaussian mapping of a non-Gaussian Probability Density Fun (PDF) through a Cell-Arc Delay Function (CADF);
FIG. 2 is a plot illustrating a multi-stage operating point;
For CMOS feature size of 65 nm and below, local (intra-die or within-die) variations in transistor Vt (threshold voltage) contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd≦0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. Existing statistical static timing analysis (SSTA) tools assume a linear Gaussian distribution for delay and thus do not provide acceptable accuracy under a non-linear, non-Gaussian situation, e.g. at very low voltage; therefore, the current static timing analysis (STA) or SSTA tools cannot achieve reasonable timing accuracy at low supply voltage.
This disclosure describes a computationally efficient algorithm for computing any desired point on the Probability Density Function (PDF) of logic Timing Path (TP) delay which results from local transistor variation. This approach will be referred to herein as Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach may be embodied using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a commercial DSP implemented in 28 nm CMOS were analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to a SPICE based Monte-Carlo analysis.
Specific embodiments of the invention will now be described in detail with reference to the accompanying figures. In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.