Compact modeling of circuit stages for static timing analysis of integrated circuit designs

A non-transitory machine readable product for timing analysis of an integrated circuit design, the non-transitory machine readable product comprising:

• a machine readable storage device having stored therein machine readable instructions
• to model a logic gate with different current source models for a steady state region of operation, a varying current region of operation, and an asymptotic region of operation;
• in response to a transition at an input of the logic gate, to determine instantaneous output current for the varying current region of operation in response to time and an instantaneous output voltage of the logic gate, and
• in response to the transition at the input of the logic gate, to determine instantaneous output current for the asymptotic region of operation in response to the instantaneous output voltage of the logic gate independent of time.

A method for analyzing timing of an integrated circuit design, the method comprising:

• with a processor
• modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation;
• in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation, wherein an instantaneous output current provided by the time varying voltage dependent current source is responsive to time and an instantaneous output voltage of the logic gate;
• and
• in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation, wherein an instantaneous output current provided by the time-invariant voltage dependent current source is responsive to the instantaneous output voltage of the logic gate independent of time.