Verification of logic circuit designs using dynamic clock gating

A system for verifying a logic circuit design using dynamic clock gating, comprising:

• a verification environment that chooses at least one master seed to determine initial values as initialization for a logic circuit and/or stimuli data for at least one interface of said logic circuit in said logic circuit design, wherein said verification environment chooses at least two different dynamic clock gating configurations for every chosen master seed and executes a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, wherein said verification environment compares against each other simulation results of the functional simulations executed with said logic circuit for said at least two different dynamic clock gating configurations chosen, and reports an error if said simulation results are not identical.