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US 8,302,036 B2Granted
Method and apparatus for designing an integrated circuit
AssigneesFreescale Semiconductor, Inc., ST Microelectronics (Crolles 2) SAS
InventorsLionel Riviere-Cazeaux, Ashish Rajput
Life of this patent
Estimating the term…
Abstract
Method and apparatus for designing an integrated circuit, IC, layout by identifying one or more defects in a feature within the IC layout. Determining if an identified defect is improvable. Calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects.
Claims13
A method of designing an integrated circuit, IC, layout comprising:
- identifying at a computer device one or more defects in a feature within the IC layout during a design stage of the IC layout;
- determining at the computer device if an identified defect is improvable by amending the feature with the identified defect and assessing if the defect has improved following amendment;
- calculating at the computer device an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects;
- comparing, at the computer device, the improvability metric with a predetermined threshold;
- reworking at the computer device the IC layout when the improvability metric exceeds the predetermined threshold;
- and
- normalising the improvability metric for wafer area.
4 more elements
A method of analysing an IC layout comprising:
- identifying at a computer device defects in the IC layout during a design stage of the IC layout;
- categorising at the computer device each identified defect according to severity of the defect;
- summing at the computer device weighted values based on the defects falling within each category to determine a weighted sum of the defects;
- calculating a manufacturability metric of the IC layout based on the weighted sum of the defects and
- normalising the manufacturability metric for wafer area.
2 more elements
Dependencies are inferred from the claim text.