Performing optical proximity correction by incorporating critical dimension correction

#1. Technical Field

#This disclosure relates generally to integrated circuit layout, and more particularly to data correcting an integrated circuit layout incorporating a critical dimension (CD) correction.

#2. Background Art

#FIG. 1 shows an example of a critical dimension (CD) error caused by two overlapping patterns where the 2nd photoresist traverses topography as it is patterned over the 1st photoresist feature.

#FIG. 2 shows a schematic block diagram of a data correction tool used to perform data correction on an IC layout.

#FIG. 3 shows a flow diagram of an example of an operation of the data correction tool of FIG. 2.

#Embodiments of this disclosure address the issues associated with double exposed structure by providing a fast and accurate approach to correct short range critical dimension (CD) variations caused by the double exposure process in an optical proximity correction (OPC) process by separating the structure design into two portions corresponding to the two exposures and implement separate OPC processes for the two portions. The resulting OPC solutions for the two portions will be combined. For the portion whose respective critical dimension (CD) will be affected by the double exposure process, a model will be generated to compensate for the CD variation over topography in the respective OPC process. In this disclosure, a short range CD variation refers to a CD variation of a specific OPC site/cell, which is contrary to a long range CD variation which represents a systematic impact of a process that affects the final wafer critical dimensions on scales larger than the optical radius in the lithography model.

#FIG. 2 shows a schematic block diagram of a data correction tool 100 used to perform a data correction on a designed IC layout for an IC structure incorporating the compensation for a short range CD variation due to a double exposure process in the fabrication of the structure according to designed layout. Data correction tool 100 comprises an input/output component 110 configured to receive input and output data. In particular, input/output component 110 is configured to receive information on designed layout and other information, such as a density map, a CD compensation map, a tape-out process flow for manufacturing a structure based on designed layout, and/or user instructions as may be required in the operation of data correction tool 100. Input/output component 110 is also configured to output results from the data correction operation. These results can be used to, e.g., generate a mask for fabricating a device.

#Data correction tool 100 further comprises a design layout separation component 120, a data correction component 130, a CD compensation model generation component 140, and a combination component 150. Design layout separation component 120 may be configured to separate a design layout into a first portion and a second portion corresponding to the double exposures required for processing the designed layout. The two exposures may be required by various situations. For example, the doubling patterning scheme may require two exposures, or the exposures of two consecutive layers may be taken as two exposures as the topography of a previous (lower) layer may affect the exposure of the immediately later (above) layer. The separation may be implemented using any technique.