System and apparatus for error-correcting register files

A computer program product comprising:

• a computer-readable storage device;
• and program code on the computer-readable storage medium that when executed by a computer device having a processor with an arithmetic logic unit, a control unit, and one or more instantiated register files provides the functions of:
• detecting the parity error associated with at least one register of a first register file and a second register that are associated with a parallel file structure, which comprises a first storage and a second storage respectively coupled to the first register file and the second register file for respectively storing a corresponding first parity value and a corresponding second parity value for each data within each register of the first register file and the second register file;
• determining which one of the first register file and the second register file contains an offending register and which one contains a non-offending register having data corresponding to the data within the offending register;
• and executing a repair sequence in response to detecting the parity error is and determining the non-offending register, wherein the register file associated with the non-offending register transmits data to the register file associated with the offending register.

A data processing system comprising:

• a processor component having a first register file that is communicatively coupled to and communicates with an arithmetic operation component and a second register file that is communicatively coupled to and communicates with a data cache, wherein the first register file and the second register file are provided redundant write data via one or more of the arithmetic operation component and the data cache, and wherein each of the first register file and the second register file comprises an array of a finite integer number of processor registers;
• a first storage coupled to the first register file and that receives data from the first register file for storage within the first storage, and a second storage coupled to the second register file and that receives data from the second register file for storage within the second storage, wherein the first register file communicates with the first storage and the second register file communicates with the second storage;
• a memory that is communicatively coupled to each of the first storage and the second storage;
• and
• one or more logic of the processor component which logic comprises code that executes to enable recovery by at least one of the first register file and the second register file from detection of a parity error, said logic including code that enables the processor component to:
• detect the parity error associated with at least one register file of a first register file and a second register file that are associated with a parallel file structure;
• determine which one of the first register file and the second register file contains an offending register and which one contains a non-offending register having data corresponding to the data within the offending register;
• and
• execute a repair sequence when the parity error is detected and the non-offending register is determined, wherein the register file associated with the non-offending register transmits data to the register file associated with the offending register.