Programmable compute unit with internal register and bit FIFO for executing Viterbi code

A system for executing a Viterbi decode on a received window of input data, the system comprising:

• an address register for storing a current address comprising a stage number and a state in a Viterbi trellis, the trellis corresponding to the received window of input data;
• a number-of-states register for storing a given Viterbi constraint length;
• a bit FIFO for storing a plurality of survivor decision words and for providing, given the current address in the address register, one survivor decision bit per cycle;
• a next-address generator for generating a next address based at least in part on the current address, the Viterbi constraint length, and the survivor decision bit by (i) subtracting a given Viterbi constraint length factor from higher-order bits of the current address and (ii) concatenating, to a result of the subtraction, lower-order bits of the current address and the survivor decision bit;
• and
• an output register for providing a decoded output stream based on bits received from the address register.

A method for executing a Viterbi decode on a received window of input data, the method comprising:

• addressing a bit FIFO using a current address to thereby read out a single survivor trace-back information bit;
• generating a next address of a state in a Viterbi trellis, the trellis corresponding to the received window of input data, by:
• i. subtracting a given Viterbi constraint length factor from higher-order bits of the current address, and
• ii. concatenating, to a result of the subtraction, lower-order bits of the current address and the survivor decision bit;
• and
• shifting a bit of a current address into an output register, the output register comprising decoded data.