Error checking parity and syndrome of a block of data with relocated parity bits
AssigneeXilinx, Inc.
InventorsWarren E. Cory, David P. Schultz, Steven P. Young
Life of this patent
Estimating the term…
Loading patent…
AssigneeXilinx, Inc.
InventorsWarren E. Cory, David P. Schultz, Steven P. Young
Estimating the term…
An apparatus for error checking is described. The apparatus includes a matrix having a plurality of bit position columns and rows, where the bit position columns are equal in number to data bits of a word length, the word length for a word serial transmission of a data vector, where the bit position columns are one each for each data bit. The bit position rows are equal in number to syndrome bits, and the bit position rows are one each for each syndrome bit. A portion of the bit position columns are allocated to parity bits for a selected word of the data vector, where the portion of the bit position columns for the selected word are one each for each parity bit allocated to the selected word.
An apparatus for error checking, comprising:
A method for error checking, comprising:
Dependencies are inferred from the claim text.