Memory system and method for providing error correction
AssigneeSamsung Electronics Co., Ltd.
InventorsNam-Phil Jo, Dae-Han Youn
Life of this patent
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Abstract
An error correction decoder includes a syndrome computation circuit, an error correction and computation circuit and an error correction circuit. The syndrome computation circuit calculates a syndrome of read data. The error correction and computation circuit calculates a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data. The error correction circuit corrects the single-bit error of the read data based on the location of the single-bit error.
Claims20
An error correction decoder comprising:
- a syndrome computation circuit for calculating a syndrome of read data;
- an error correction and computation circuit for calculating a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data;
- and
- an error correction circuit for correcting the single-bit error of the read data based on the location of the single-bit error.
A method of correcting an error of circuit code data comprising:
- computing a syndrome of read data;
- determining when the read data includes an error and whether the error of the read data is a one-bit error, based on the syndrome;
- when the error of the read data is a one-bit error, obtaining an error location using a division operation of consecutive elements of the syndrome;
- and
- correcting the error of the read data based upon the error location.
A memory system comprising:
- a non-volatile memory device;
- and
- a memory controller comprising an error correction code (ECC) circuit for eliminating an error from read data of the non-volatile memory device, wherein the ECC circuit comprises:
- a syndrome computation circuit for computing a syndrome from the read data;
- an error correction and computation circuit for computing a location of the error of the read data using a division operation between elements of the syndrome, when the error is a single-bit error;
- and
- an error correction circuit for correcting the error of the read data with reference to the error location.
Dependencies are inferred from the claim text.