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US 8,301,977 B2Granted
Accelerating phase change memory writes
AssigneeSTMicroelectronics S.r.l.
InventorsMeenatchi Jagasivmani, Anthony Ko, Rich E. Fackenthal, Ferdinando Bedeschi, Enzo Donze, Ravi Gutala
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Abstract
In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.
Claims28
A method comprising:
- writing to a phase change memory using a software control;
- and
- accelerating the writing to the phase change memory using a hardware accelerator, wherein using a hardware accelerator includes:
- detecting a reduction in set current;
- and
- generating an address to a phase change memory array of the phase change memory in response to the detection of the reduction of set current.
3 more elements
A method comprising:
- writing to a phase change memory using a software control;
- accelerating the writing to the phase change memory using a hardware accelerator;
- and
- locating errors at bits of the phase change memory array, wherein locating errors includes reading a memory word from a memory location, using an error correction code to generate a correction signature for at least a portion of the memory word, generating a corrected word from the memory word and from the correction signature and comparing the corrected word with the memory word.
1 more element
A phase change memory comprising:
- a memory array including phase change memory cells;
- and
- a hardware accelerator configured to accelerate writing data to the phase change memory array, wherein said hardware accelerator includes:
- a detector configured to detect a reduction in a set current and
- an address generator configured to output an address of a next memory cell to be programmed in response receiving an indication from the detector indicating that the detector has detected the reduction in the set current.
2 more elements
A phase change memory comprising:
- a memory array including phase change memory cells;
- a hardware accelerator configured to accelerate writing data to the phase change memory array;
- an error correction module configured to locate errors at bits of said memory array;
- and
- a controller configured to selectively modify bits at which errors have been located, wherein said error correction module is configured to receive a memory word from a memory location, to use an error correction code to generate a correction signature for at least a portion of said memory word, to generate a corrected word from said memory word and from said correction signature and to compare said corrected word with said memory word.
2 more elements
A system comprising:
- a processor;
- and
- a phase change memory coupled to said processor, said phase change memory including a memory array including phase change memory cells and a hardware accelerator to accelerate writing data to said phase change memory array, wherein said hardware accelerator includes:
- a detector configured to detect a reduction in a set current and
- an address generator configured to output an address of a next memory cell to be programmed in response receiving an indication from the detector indicating that the detector has detected the reduction in the set current.
2 more elements
A system comprising:
- a processor;
- and
- a phase change memory coupled to said processor, said phase change memory including:
- a memory array including phase change memory cells;
- a hardware accelerator configured to accelerate writing data to the phase change memory array;
- an error correction module configured to locate errors at bits of said memory array;
- and
- a controller configured to selectively modify bits at which errors have been located, wherein the error correction module is configured to receive a memory word from a memory location, to use an error correction code to generate a correction signature for at least a portion of the memory word, to generate a corrected word from the memory word and from the correction signature, and to compare the corrected word with the memory word.
5 more elements
Dependencies are inferred from the claim text.