Apparatus for correcting single bit insertion or deletion in a data payload with a checksum corrector
AssigneeSeagate Technology LLC
InventorYawshing Tang
Life of this patent
Estimating the term…
Abstract
This application discloses a message format including a data payload of N bits and a corrector component encoding a checksum to correct the checksum of single bit slipping noise, where the checksum is the sum of each data payload bit by its position modulo N+1. The corrector component may encode a second checksum derived from the checksum that may also be included in the message and so on. Apparatus embodiments may include a transmitter generating a transmitted message of this format and/or a receiver using a received message that may be corrupted from the transmitted message through bit slipping in the form of bit insertion or bit deletion.
Claims19
A system, comprising:
- a transmitter configured to transmit a message via a communicative coupling to a receiver, the message susceptible to corruption by single bit transmission error and comprising:
- a data payload comprising N bits;
- a checksum comprising J bits, wherein said checksum is a sum modulo N+1, the sum is a sum of products, and each product is a product of each data payload bit multiplied by a position of each data payload bit;
- and
- a corrector component encoding said checksum to correct said single bit transmission error in said checksum to correctly determine said checksum.
A device, comprising:
- a receiver including a processor configured to receive and operate upon a transmitted message susceptible to single bit transmission error, the transmitted message comprising:
- a data payload comprising N bits;
- a checksum comprising J bits, wherein said checksum is a sum modulo N+1, the sum is a sum of products, and each product is a product of each data payload bit multiplied by a position of each data payload bit;
- and
- a corrector component encoding said checksum to correct said single bit transmission error in said checksum to correctly determine said checksum;
- wherein said processor is configured to implement a checksum error correction-detection process on the transmitted message received by the receiver (received message) to generate a received data output corrected of said single bit transmission error.
A device, comprising:
- a processor configured to create a transmitted message susceptible to corruption by single bit transmission error, the transmitted message comprising:
- a data payload comprising N bits;
- a checksum comprising J bits, wherein said checksum is a sum modulo N+1, the sum is a sum of products, and each product is a product of each data payload bit multiplied by a position of each data payload bit;
- and
- a corrector component encoding said checksum to correct said single bit transmission error in said checksum to correctly determine said checksum.
A method, comprising:
- generating a transmitted message, wherein said transmitted message is susceptible to a single bit transmission error and includes a data payload comprising N bits, a checksum comprising J bits, and a corrector component encoding said checksum to correct the effect of said single bit transmission error on said checksum;
- receiving the transmitted message;
- and
- generating a received data output using the received transmitted message wherein generating the received data output further comprises:
- decoding a corrected checksum with a received version of said corrector component to create a corrected checksum without said single bit transmission error;
- and
- reverse calculating using a received version of said data payload and said corrected checksum to create said received data output as said data payload without said single bit transmission error.
Dependencies are inferred from the claim text.