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US 8,301,970 B2Granted
Sequential circuit with error detection
AssigneeIntel Corporation
InventorsKeith Bowman, James Tachanz, Nam Sung Kim, Janice Lee, Chris Wilkerson, Shih-Lien L. Lu, Tanay Karnlk, Vivek De
Life of this patent
Estimating the term…
Abstract
Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
Claims18
A chip comprising:
- a latch with an output and an input that is blocked from the output during a first clock phase and transparent to the output during a second clock phase;
- and
- a transition detector having a single pulse generator coupled to the input to assert a signal if a transition occurs at the input during the second clock phase but not to assert during the first clock phase.
A chip comprising:
- a processing core having a pipeline stage with a datapath including a latch to receive data at an input during a first clock phase and to provide the received data at an output of the latch during a second clock phase, and
- a transition detector having a single pulse generator coupled to the latch to initiate an error correction if the data arrives at the input during the second clock phase and not to initiate any error correction during the first clock phase, the data being passed to the output during the second phase even if it arrives at the input during the second phase.
A system comprising:
- a processor comprising a processing core having a pipeline stage with a datapath including:
- a latch to receive data at an input during a first clock phase and to provide the received data at an output of the latch during a second clock phase, and
- a transition detector having a single pulse generator coupled to the latch to initiate an error correction if the data arrives at the input during the second clock phase and not to initiate any error correction during the first clock phase, the data being passed to the output during the second phase even if it arrives at the input during the second phase;
- and
- an antenna coupled to the processor to communicatively link the processor to a wireless network.
2 more elements
Dependencies are inferred from the claim text.