Decompressors for low power decompression of test patterns
AssigneeMentor Graphics Corporation
InventorsJanusz Rajski, Grzegorz Mrugalski, Dariusz Czysz, Jerzy Tyszer
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Abstract
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
Claims20
An apparatus, comprising:
- a linear finite state machine (LFSM) having two or more LFSM outputs and one or more LFSM inputs;
- a register comprising two or more register inputs and two or more register outputs, the two or more register inputs being respectively coupled to the two or more LFSM outputs;
- and
- a phase shifter comprising two or more phase shifter inputs and two or more phase shifter outputs, the two or more phase shifter inputs being respectively coupled to the two or more register outputs.
One or more non-transitory computer-readable storage devices storing design data for implementing an apparatus, the apparatus comprising:
- a linear finite state machine (LFSM) having two or more LFSM outputs and one or more LFSM inputs;
- a register comprising two or more register inputs and two or more register outputs, the two or more register inputs being respectively coupled to the two or more LFSM outputs;
- and
- a phase shifter comprising two or more phase shifter inputs and two or more phase shifter outputs, the two or more phase shifter inputs being respectively coupled to the two or more register outputs.
One or more non-transitory computer-readable storage devices storing computer-executable instructions which when executed will cause a computer system to perform a method, the method comprising:
- generating circuit design information for decompression circuitry, the circuit design information defining:
- a linear finite state machine (LFSM) having two or more LFSM outputs and one or more LFSM inputs;
- a register comprising two or more register inputs and two or more register outputs, the two or more register inputs being respectively coupled to the two or more LFSM outputs;
- and
- a phase shifter comprising two or more phase shifter inputs and two or more phase shifter outputs, the two or more phase shifter inputs being respectively coupled to the two or more register outputs.
Dependencies are inferred from the claim text.