State machine select inputs coupled to TDI, TCK, and TMS

An integrated circuit comprising:

• A. a test data in lead, a test clock lead, a test mode select lead, and a test data out lead;
• B. a state machine having an input connected to the test clock lead, an input connected to the test mode select lead, and a select input coupled to select input leads, the state machine having control outputs;
• C. a register having an input connected to the test data in lead and an output coupled to the test data out lead, the register having control inputs connected to the state machine control outputs, and having enable outputs;
• and
• D. test circuitry, separate from the state machine and register, coupled to the test data in lead, the test clock lead, the test mode select lead, and the test data out lead and having select outputs connected to the select input leads.