Pulse flop with enhanced scan implementation

A flop comprising:

• a pulse-triggered storage device coupled to receive a pulse clock and configured to capture a value on an input to the pulse-triggered storage device responsive to a pulse on the pulse clock, wherein the pulse clock is derived from a first clock, and wherein a width of the pulse is less than 10% of a width of a phase of the first clock during use;
• a latch coupled to receive a scan data input, wherein the latch is configured to be open in a first phase of a clock cycle of a clock that controls the flop and to be closed in a second phase of the clock cycle, wherein a pulse supplied to the pulse-triggered storage device occurs in the second phase;
• and
• a circuit configured to supply a latched scan data input signal from the latch to the input of the pulse-triggered storage device.

An integrated circuit comprising:

• a plurality of pulse flops, each having a scan data input and a scan data output, wherein the scan data inputs are coupled to the scan data outputs in a serial fashion to form a scan chain;
• a clock generator circuit configured to generate a clock input to the plurality of pulse flops;
• wherein each of the plurality of pulse flops comprises a clock control circuit configured to generate a pulse responsive to the clock input, wherein the storage circuit is configured to capture state responsive to the pulse, and wherein the clock control circuit comprises an odd number of inverter circuits coupled in series and coupled to receive the clock input, and wherein the clock control circuit further comprises a logic circuit coupled to receive the clock input and an output of the series-coupled inverters, and wherein the logic circuit is configured to generate the pulse between a first edge of the clock input and a corresponding edge output from the series-coupled inverters;
• and
• a scan control circuit coupled to provide a scan enable signal to the plurality of pulse flops;
• wherein each of the plurality of pulse flops comprises a latch coupled to receive the scan data input and coupled to provide a latched scan data input to a storage circuit of the flop, wherein the storage circuit is configured to capture a state of the latched scan data input responsive to assertion of the scan enable from the scan control circuit.

A method comprising:

• latching a scan data input to a clocked storage device in a latch within the clocked storage device during a first phase of a clock cycle;
• pulsing a storage circuit within the clocked storage device during a second phase of the clock cycle different from the first phase, wherein the storage circuit is configured to capture a value on an input to the storage circuit responsive to a pulse on a pulse clock input of the storage circuit, wherein the pulse clock is derived from a first clock that defines the clock cycle, and wherein a width of the pulse is less than 10% of a width of the second phase;
• and
• capturing the latched scan data input in the storage circuit responsive to the pulsing and further responsive to a scan enable input to the clocked storage device.