Memory controller with loopback test interface

An apparatus comprising:

• an interconnect;
• a processor coupled to the interconnect;
• and
• a memory controller coupled to the interconnect, wherein the memory controller is programmable by the processor into a loopback test mode of operation, and wherein, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect, and wherein the memory controller is configured to route write data from the first write operation through a plurality of drivers and a plurality of receivers configured to couple to one or more memory modules controlled by the memory controller during use, and wherein the memory controller is configured to capture the write data from the plurality of receivers in a first buffer, and wherein the memory controller is configured to return the captured write data as read data on the interconnect for a first read operation received from the processor on the interconnect, wherein the memory controller further comprises a read data buffer, and wherein data returned from the memory controller in response to the first read operation is routed by the memory controller from the first buffer through the plurality of drivers and receivers to the read data buffer, and wherein the memory controller is configured to drive the data from the read data buffer onto the interconnect, wherein a read address from the first read operation is compared to addresses of the write data in the first buffer to determine which data to provide to the read data buffer in response to the first read operation, wherein the memory controller further comprises a second plurality of drivers and a second plurality of receivers, wherein the second plurality of drivers are configured to drive address bits to the one or more memory modules, and wherein the second plurality of receivers are configured to provide address bits to the first buffer in the loopback test mode.

A method comprising:

• receiving a first write operation from a processor over an interconnect to a memory controller in a loopback test mode of operation;
• routing write data from the first write operation through a plurality of drivers and a plurality of receivers in the memory controller, wherein the plurality of drivers and the plurality of receivers are configured to couple to one or more memory modules;
• capturing the write data from the plurality of receivers in the memory controller as captured data in a first buffer;
• receiving a first read operation from the processor over the interconnect to the memory controller in the loopback test mode of operation;
• returning the captured data as read data on the interconnect for the first read operation received from the processor on the interconnect, wherein the returning comprises reading the captured data from the first buffer and transmitting the captured data through the plurality of drivers and the plurality of receivers prior to returning the captured data to on the interconnect, wherein the memory controller further comprises a second plurality of drivers and a second plurality of receivers, wherein the second plurality of drivers are configured to drive address bits to the one or more memory modules, and wherein the second plurality of receivers are configured to provide address bits to the first buffer;
• and
• comparing address bits from the second plurality of receivers to addresses in the first buffer.