Apparatus and method for performing a screening test of semiconductor integrated circuits

A method of performing a screening test of a semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, wherein said processors are programmatically operable at a first synchronization clock, said method comprising:

• upon receipt of all instruction read requests from said processors, reading instructions from a memory, and outputting the instructions to said respective processors at said first synchronization clock of said processors in synchronization with each other;
• upon receipt of all data read requests from said processors, reading data from a memory, and outputting the data to said respective processors at a second synchronization clock of said processors in synchronization with each other;
• and
• comparing instruction execution information at a third synchronization clock of said processors, which information is output from the respective processors to determine whether or not any of said processors has output different instruction execution information.

A computer program product for causing a computer to perform a screening test of a semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, wherein said processors are programmatically operable at a first synchronization clock, said computer program product comprising:

• software instructions for causing said computer to perform a predetermined procedure;
• and
• a computer-readable medium for recording therein said software instructions, said predetermined procedure including the steps of:
• upon receipt of all instruction read requests from said processors, reading instructions from a memory, and outputting the instructions to said respective processors at said first synchronization clock of said processors in synchronization with each other;
• upon receipt of all data read requests from said processors, reading data from a memory, and outputting the data to said respective processors at a second synchronization clock of said processors in synchronization with each other;
• and
• comparing instruction execution information at a third synchronization clock of said processors, which information is output from the respective processors at each operating cycle of said processors to determine whether or not any of said processors has output different instruction execution information.