Multi-clock asynchronous logic circuits
AssigneeAchronix Semiconductor Corporation
InventorsRajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Gael Paul, Raymond Nijssen, Marcel Van der Goot
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Abstract
Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.
Claims28
A processor-implemented method to execute on one or more processors that perform the method, comprising:
- associating at least one data token with a clock domain of a multi-clock domain netlist of a synchronous circuit design;
- determining a durational relationship between clock periods associated with the clock domain and at least one other clock domain of the multi-clock domain netlist;
- transforming the at least one data token when using the at least one data token in the at least one other clock domain, based on the relationship;
- and
- converting the multi-clock domain netlist of the synchronous circuit design into an asynchronous representation using the at least one data token being transformed.
A system comprising:
- memory to store a plurality of modules;
- and
- one or more processors coupled to the memory to execute the plurality of modules including:
- an association module to associate at least one data token with a clock domain of a multi-clock domain netlist of a synchronous circuit design;
- a determination module to determine a durational relationship between clock periods associated with the clock domain and at least one other clock domain of the multi-clock domain netlist;
- and
- a transformation module to transform the at least one data token when using the at least one data token in the at least one other clock domain, based on the relationship, the transformation module configured to convert the multi-clock domain netlist of the synchronous circuit design into an asynchronous representation using the at least one data token being transformed.
A non-transitory machine-readable medium comprising instructions, which when executed by one or more processors, perform a method comprising:
- associating at least one data token with a clock domain of a multi-clock domain netlist of a synchronous circuit design;
- determining a durational relationship between clock periods associated with the clock domain and at least one other clock domain of the multi-clock domain netlist;
- transforming the at least one data token when using the at least one data token in the at least one other clock domain, based on the relationship;
- and
- converting the multi-clock domain netlist of the synchronous circuit design into an asynchronous representation using the at least one data token being transformed.
A processor-implemented method to execute on one or more processors that perform the method comprising:
- converting a synchronous multi-clock domain circuit design into an asynchronous representation by
- generating a multi-clock domain netlist of the synchronous circuit design;
- and
- converting the multi-clock domain netlist into an asynchronous representation, the converting comprising:
- associating at least one data token with a clock domain of the multi-clock domain netlist;
- determining a durational relationship between clock periods associated with the clock domain and at least one other clock domain of the multi-clock domain netlist;
- and
- transforming the at least one data token when using the at least one data token in the at least one other clock domain, based on the relationship.
Dependencies are inferred from the claim text.