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US 8,301,916 B2Granted
Method and apparatus for a computing system having an active sleep mode CPU that uses the cache of a normal active mode CPU
AssigneeIntel Corporation
InventorTony G. Hamilton
Life of this patent
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Abstract
A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.
Claims11
An apparatus, comprising:
- a first processor unit to operate in a first, higher power mode;
- a second processor unit to operate in a second, lower power mode, the second processor unit to have access to a lesser number of available instructions than the first processor unit;
- a main memory to store instructions to be executed by the first processor unit;
- a memory cache that is accessible to the first and second processor units, wherein the memory cache stores instructions to be executed by the second processor unit in the second, lower power mode and the second processor unit and memory cache to be active when the first processor unit and main memory are not active.
1 more element
Dependencies are inferred from the claim text.