US 8,301,865 B2 · System and method to manage address translation requests

Abstract

A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush.

Claims20

Dependent claims

A method, comprising:

using a computer to perform:
storing data in one or more entries in a pending request queue comprising:
an instruction-related portion configured to store entries corresponding to pending address translations associated with instruction translation lookaside buffer (ITLB) misses;
and
a data-related portion configured to store entries corresponding to address translations associated with potential or actual data translation lookaside buffer (DTLB) misses;
selecting an address translation to be serviced from among address translations associated with a plurality of entries in the pending request queue, wherein said selecting is dependent on one or more prior address translation selections;
allocating an entry associated with the selected address translation in a translation table entry return queue configured to store translation table entry responses;
and
servicing the selected address translation.

6 more elements

A processor, comprising:

a memory management unit configured to:
store data in one or more entries in a pending request queue comprising:
an instruction-related portion configured to store entries corresponding to pending address translations associated with instruction translation lookaside buffer (ITLB) misses;
and
a data-related portion configured to store entries corresponding to address translations associated with potential or actual data translation lookaside buffer (DTLB) misses;
select an address translation to be serviced from among address translations associated with a plurality of entries in the pending request queue, wherein said selecting is dependent on one or more prior address translation selections;
allocate an entry associated with the selected address translation in a translation table entry return queue configured to store translation table entry responses;
and
service the selected address translation.

6 more elements

A system, comprising:

a processor;
and
a memory coupled to the processor and storing instructions executable by the processor;
wherein the processor comprises a memory management unit configured to:
store data in one or more entries in a pending request queue comprising:
an instruction-related portion configured to store entries corresponding to pending address translations associated with instruction translation lookaside buffer (ITLB) misses;
and
a data-related portion configured to store entries corresponding to address translations associated with potential or actual data translation lookaside buffer (DTLB) misses;
select an address translation to be serviced from among address translations associated with a plurality of entries in the pending request queue, wherein said selecting is dependent on one or more prior address translation selections;
allocate an entry associated with the selected address translation in a translation table entry return queue configured to store translation table entry responses;
and
service the selected address translation.

9 more elements

Dependencies are inferred from the claim text.

System and method to manage address translation requests

Life of this patent

System and method to manage address translation requests

Life of this patent

Abstract

Claims20