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US 8,301,856 B2Granted
Restricting memory areas for an instruction read in dependence upon a hardware mode and a security flag
AssigneeArm Limited
InventorRichard Roy Grisenthwaite
Life of this patent
Estimating the term…
Abstract
An apparatus for processing data 2 includes a processor 8, a memory 6 and memory control circuitry 12. The processor 8 operates in a plurality of hardware modes including a privileged mode and a user mode. When operating in the privileged mode, the processor 8 is blocked by the memory control circuitry 12 from fetching instructions from memory address regions 34, 38, 42 within the memory 6 which are writeable within the user mode if a security flag within register 46 is set to indicate that this blocking mechanism is active.
Claims13
Apparatus for processing data comprising:
- a processor responsive to a stream of program instructions to perform processing operations;
- and
- memory control circuitry coupled to said processor and to a memory and configured to control access to said memory by said processor;
- wherein
- said processor has a plurality of hardware modes of operation including at least a first mode and a second mode;
- said memory control circuitry controls access to said memory such that:
- (i) when said processor is in said first mode, said memory control circuitry permits write access to a first portion of said memory and does not permit at least write access to a second portion of said memory;
- and
- (ii) when said processor is in said second mode, said memory control circuitry permits write access to said first portion of said memory and permits write access to a second portion of said memory;
- and
- said memory control circuitry is responsive to a security flag having a set value to give said processor in said first mode an execution access not given to said processor in said second mode by preventing said processor reading, from said first portion of said memory, program instructions for execution by said processor in said second mode, wherein when said security flag has said set value and said processor is in said second mode, said memory control circuitry permits said processor to read data values from said first portion of said memory.
8 more elements
Apparatus for processing data comprising:
- processor means for performing processing operations in response to a stream of program instructions;
- and
- memory control means circuitry coupled to said processor means and to a memory means for storing data for controlling access to said memory means by said processor means;
- wherein
- said processor means has a plurality of hardware modes of operation including at least a first mode and a second mode;
- said memory control means controls access to said memory means such that:
- (i) when said processor means is in said first mode, said memory control means permits write access to a first portion of said memory means and does not permit at least write access to a second portion of said memory means;
- and
- (ii) when said processor means is in said second mode, said memory control means permits write access to said first portion of said memory means and permits write access to a second portion of said memory means;
- and
- said memory control means is responsive to a security flag having a set value to give said processor means in said first mode an execution access not given to said processor means in said second mode by preventing said processor means reading, from said first portion of said memory means, program instructions for execution by said processor means in said second mode, wherein when said security flag has said set value and said processor means is in said second mode, said memory control circuitry permits said processor means to read data values from said first portion of said memory means.
8 more elements
A method of processing data, said method comprising the steps of:
- performing processing operations with a processor in response to a stream of program instructions;
- and
- controlling access to a memory by said processor using memory control circuitry coupled to said processor and to said memory;
- wherein
- said processor has a plurality of hardware modes of operation including at least a first mode and a second mode;
- said memory control circuitry controls access to said memory such that:
- (i) when said processor is in said first mode, said memory control circuitry permits write access to a first portion of said memory and does not permit at least write access to a second portion of said memory;
- and
- (ii) when said processor is in said second mode, said memory control circuitry permits write access to said first portion of said memory and permits write access to a second portion of said memory;
- and
- said memory control circuitry is responsive to a security flag having a set value to give said processor in said first mode an execution access not given to said processor in said second mode by preventing said processor reading, from said first portion of said memory, program instructions for execution by said processor in said second mode, wherein when said security flag has said set value and said processor is in said second mode, said memory control circuitry permits said processor to read data values from said first portion of said memory.
8 more elements
Dependencies are inferred from the claim text.