Memory system which writes data to multi-level flash memory by zigzag interleave operation
AssigneeKabushiki Kaisha Toshiba
InventorsShinji Kawano, Kazunori Sato, Hitoshi Shimono, Eriko Chiba
Life of this patent
Estimating the term…
Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorsShinji Kawano, Kazunori Sato, Hitoshi Shimono, Eriko Chiba
Estimating the term…
According to one embodiment, a memory system includes a first memory chip includes a first temporary memory and a first block, a second memory chip includes a second temporary memory and a second block, and a memory controller that controls writing of logical pages to the first and second memory chips. The memory controller forms a second unit having the same page number as the first unit by the first temporary memory and the lowermost physical page in the first block, forms a third unit having the same page number as the first unit by the second temporary memory and the lowermost physical page in the second block, and writes the logical pages by an interleave operation in order of the second unit, the third unit, the first unit in the first block, and the first unit in the second block.
A memory system comprising:
Dependencies are inferred from the claim text.