Systems and methods for reliable multi-level cell flash storage

A multi-level cell (MLC) flash memory comprising:

• a critical portion and a non-critical portion, each portion comprising a plurality of memory cells;
• wherein data stored in each memory cell in the non-critical portion is stored in one of a plurality of MLC states, said plurality including a highest MLC state and a lowest MLC state;
• and
• wherein data stored in each memory cell in the critical portion is stored in either the highest MLC state or the lowest MLC state, wherein the MLC flash memory is a 3BPC flash memory and a 111 MLC state is the highest MLC state and a 000 MLC state is the lowest MLC state.

A method of reading multi-level cell (MLC) flash memory having a critical portion and a non-critical portion comprising:

• receiving a memory address;
• reading data at the memory address;
• determining whether the memory address is in the critical portion;
• if the memory address is in the critical portion, assigning a binary value to each MLC state read from the data stored at the memory address;
• and
• wherein a first binary value is assigned if the MLC state read has an associated threshold voltage greater than a central cutoff threshold voltage and a second binary value is assigned if the MLC state read has an associated threshold voltage less than a central cutoff threshold voltage.