Data read method for processing a plurality of host read commands, and flash memory controller and storage system using the same

A flash memory controller, for processing a plurality of host read commands from a host system to read data corresponding to the host read commands from a plurality of flash memory modules, wherein each of the flash memory modules has a plurality of physical blocks, the flash memory controller comprising:

• a microprocessor unit;
• a flash memory interface unit, coupled to the microprocessor unit and coupled to the flash memory modules through a plurality of data input/output buses;
• a host interface unit, coupled to the microprocessor unit and connected to the host system;
• and
• a memory management unit, coupled to the microprocessor unit and wherein the memory management unit configures a plurality of logical blocks, wherein the logical blocks are mapped to a part of the physical blocks in the flash memory modules,
• wherein the memory management unit receives command queuing information related to the host read commands from the host system through the host interface unit, wherein each of the host read commands corresponds to one of the logical blocks, and each of the logical blocks corresponds to one of the data input/output buses,
• wherein the memory management unit re-arranges the host read commands, generates a command giving sequence according to the data input/output buses corresponding to the host read commands and sends the command giving sequence to the host system,
• wherein the memory management unit sequentially receives the host read commands from the host system through the host interface unit according to the command giving sequence and reads the data corresponding to the host read commands from the flash memory modules through the flash memory interface unit according to the host read commands.

A flash memory storage system, comprising:

• a flash memory chip, having a plurality of flash memory modules, wherein each of the flash memory modules has a plurality of physical blocks;
• a flash memory controller, coupled to the flash memory modules through a plurality of data input/output buses, wherein the flash memory controller configures a plurality of logical blocks, wherein the logical blocks are mapped to a part of the physical blocks in the flash memory modules;
• and
• a connector, coupled to the flash memory controller, and coupled to a host system,
• wherein the flash memory controller receives command queuing information related to a plurality of host read commands from the host system through the connector, wherein each of the host read commands corresponds to one of the logical blocks, and each of the logical blocks corresponds to one of the data input/output buses,
• wherein the flash memory controller re-arranges the host read commands and generates a command giving sequence according to the data input/output buses corresponding to the host read commands and sends the command giving sequence to the host system,
• wherein the flash memory controller sequentially receives the host read commands from the host system through the connector according to the command giving sequence and reads data corresponding to the host read commands from the flash memory modules through the data input/output buses according to the host read commands.