Divider for fixed point division

Electronic hardware adapted to divide a dividend by a divisor in a fixed point representation including one or more electronic components for:

• storing a divisor in a first storage space,
• storing a dividend in a second storage space,
• storing a preliminary answer initialized to zero in a third storage space,
• subtracting the divisor from the dividend to produce a result, and
• computing an answer to the division of the divider by revising the dividend and preliminary answer during a number of iterations of the subtracting step until a required precision is reached, wherein the revising step includes:
• in the event of no overflow from the subtractor, left shifting the result 1 bit, removing the most significant bit of the result, left shifting the preliminary answer in the third storage space 1 bit, removing the most significant bit of the preliminary answer, loading the least significant bit of the result with the most significant bit of the preliminary answer, loading 1 into the least significant bit of the preliminary answer, and storing the revised result in the second storage space;
• in the event of overflow from the subtractor, left shifting the dividend 1 bit, removing the most significant bit of the dividend, left shifting the preliminary answer in the third storage space 1 bit, removing the most significant bit of the preliminary answer, replacing the least significant bit of the dividend with the most significant bit of the preliminary answer, loading 0 into the least significant bit of the preliminary answer, and storing the revised dividend in the second storage space;
• and
• upon completion of the iterations, outputting the preliminary answer in the third storage space as the answer to the division;
• wherein the divisor and the dividend are in the range (−1,1);
• and
• wherein the divider is adapted to insert a decimal place in the answer.

A method for dividing a dividend by a divisor to provide an answer, comprising the steps of:

• storing the divisor and dividend in first and second storage spaces in a memory;
• subtracting the divisor from the dividend in a subtractor circuit to produce a result,
• revising the dividend and a preliminary answer initialised to zero based on the result, and storing the revised dividend in the second storage space in the memory,
• storing the preliminary answer in a third storage space in the memory, and
• reiterating the subtracting and revising steps multiple times until a required precision is reached, based on a revised dividend and revised preliminary answer obtained each iteration,
• wherein the dividend, result, and preliminary answer are in binary form and the dividend and preliminary answer are revised by:
• a) in the event of no overflow from the subtraction, left shifting the result 1 bit, removing the most significant bit of the result, left shifting the preliminary answer 1 bit in the third storage space in the memory, removing the most significant bit of the preliminary answer, loading the least significant bit of the result with the most significant bit of the preliminary answer, loading 1 into the least significant bit of the preliminary answer, and storing the revised result in the second storage space;
• or
• b) in the event of overflow from the subtractor circuit, left shifting the dividend 1 bit, removing the most significant bit of the dividend, left shifting the preliminary answer 1 bit in the third storage space in the memory, removing the most significant bit of the preliminary answer, replacing the least significant bit of the dividend with the most significant bit of the preliminary answer, loading 0 into the least significant bit of the preliminary answer, and storing the revised dividend in the second storage space;
• outputting the preliminary answer from the third storage space as the answer upon ceasing the reiterations;
• and
• inserting a decimal place in the answer;
• wherein the divisor and the dividend are in the range (−1,1).