Host cell spatially aware emulation of a guest wild branch
AssigneeInternational Buisness Machines Corporation
InventorsTheodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
Life of this patent
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Abstract
A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed.
Claims22
A computer program product for emulating execution of Guest processor instructions on a Host processor, the Host processor configured to execute Host instructions of a Host instruction set, wherein the Guest instructions to be emulated are not instructions of the Host instruction set, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- creating, by the Host processor, a cell association wherein each of m Guest cells of Guest addressable memory are associated with a corresponding Host cell of m Host cells of Host addressable memory, said m Guest cells comprising first Guest cells, each first Guest cell corresponding to a beginning portion of a Guest instruction to be emulated, wherein long Guest instructions occupy a plurality of Guest cells consisting of said first Guest cell and one or more second Guest cells, wherein each Guest cell is x bytes of memory, wherein each Host cell is y bytes of memory, wherein each first Host cell comprises a semantic routine for performing function of an Guest instruction of a corresponding first Guest cell, wherein each second Host cell comprises a wild branch handling routine for performing a wild branch function according to a Guest computer architecture;
- responsive to initiating emulation of a program counter specified Guest instruction at a program counter specified Guest cell corresponding to a program counter location, causing a routine in a specified Host cell corresponding to the specified Guest cell to be executed comprising:
- based on the specified Host cell being a first Host cell corresponding to a first Guest cell, executing the semantic routine of the specified Host cell to perform function of the Guest instruction;
- and
- based on the specified Host cell being a second Host cell corresponding to a second Guest cell, executing the wild branch handling routine of the specified Host cell to perform the wild branch function.
A computer system for emulating execution of Guest processor instructions on a Host processor, the Host processor configured to execute Host instructions of a Host instruction set, wherein the Guest instructions to be emulated are not instructions of the Host instruction set, the computer system comprising:
- a memory;
- and
- a processor in communication with the memory, the computer system configured to perform a method comprising:
- creating, by the Host processor, a cell association wherein each of m Guest cells of Guest addressable memory are associated with a corresponding Host cell of m Host cells of Host addressable memory, said m Guest cells comprising first Guest cells, each first Guest cell corresponding to a beginning portion of a Guest instruction to be emulated, wherein long Guest instructions occupy a plurality of Guest cells consisting of said first Guest cell and one or more second Guest cells, wherein each Guest cell is x bytes of memory, wherein each Host cell is y bytes of memory, wherein each first Host cell comprises a semantic routine for performing function of an Guest instruction of a corresponding first Guest cell, wherein each second Host cell comprises a wild branch handling routine for performing a wild branch function according to a Guest computer architecture;
- responsive to initiating emulation of a program counter specified Guest instruction at a program counter specified Guest cell corresponding to a program counter location, causing a routine in a specified Host cell corresponding to the specified Guest cell to be executed comprising:
- based on the specified Host cell being a first Host cell corresponding to a first Guest cell, executing the semantic routine of the specified Host cell to perform function of the Guest instruction;
- and
- based on the specified Host cell being a second Host cell corresponding to a second Guest cell, executing the wild branch handling routine of the specified Host cell to perform the wild branch function.
A computer implemented method for emulating execution of Guest processor instructions on a Host processor, the Host processor configured to execute Host instructions of a Host instruction set, wherein the Guest instructions to be emulated are not instructions of the Host instruction set, for emulating execution of wild branches of a Guest processor instructions on a Host processor, the method comprising:
- creating, by the Host processor, a cell association wherein each of m Guest cells of Guest addressable memory are associated with a corresponding Host cell of m Host cells of Host addressable memory, said m Guest cells comprising first Guest cells, each first Guest cell corresponding to a beginning portion of a Guest instruction to be emulated, wherein long Guest instructions occupy a plurality of Guest cells consisting of said first Guest cell and one or more second Guest cells, wherein each Guest cell is x bytes of memory, wherein each Host cell is y bytes of memory, wherein each first Host cell comprises a semantic routine for performing function of an Guest instruction of a corresponding first Guest cell, wherein each second Host cell comprises a wild branch handling routine for performing a wild branch function according to a Guest computer architecture;
- responsive to initiating emulation of a program counter specified Guest instruction at a program counter specified Guest cell corresponding to a program counter location, causing a routine in a specified Host cell corresponding to the specified Guest cell to be executed comprising:
- based on the specified Host cell being a first Host cell corresponding to a first Guest cell, executing the semantic routine of the specified Host cell to perform function of the Guest instruction;
- and
- based on the specified Host cell being a second Host cell corresponding to a second Guest cell, executing the wild branch handling routine of the specified Host cell to perform the wild branch function.
A computer program product for emulating execution of wild branches of Guest processor instructions of a Guest processor instruction set architecture on a Host processor of a Host instruction set architecture, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- emulating, by the Host processor, execution of Guest processor instructions, the emulation comprising:
- for Guest processor instructions, associating a Host cell of Host memory with each portion of a Guest processor instruction, wherein at least one Guest instruction consists of a plurality of portions, wherein portions consists of a single number of bytes, wherein portions are addressable by a Guest program counter (Gpc) value of a Gpc;
- using the Gpc value to locate Host cells, wherein each Host cell consists of any one of an emulation cell, or a wild branch cell, wherein the emulation cell contains a semantic routine of Host instructions for emulating execution of the Guest instruction or a wild branch cell, wherein the wild branch cell contains a wild branch routine of Host instructions for handling a branch to a location within the Guest instruction;
- based on the Gpc value being an address of a first portion of a Guest processor instruction, executing a corresponding Host semantic routine of the located Host cell for emulating the Guest instruction;
- and
- based on the Gpc value being an address of a second portion of the Guest processor instruction, executing a corresponding wild branch routine of the Host cell.
Dependencies are inferred from the claim text.