Compactor independent fault diagnosis

One or more computer-readable memory or storage devices media storing computer-executable instructions which, when executed by a computer, cause the computer to perform a method, the method comprising:

• receiving a compressed failing response, the compressed failing response having been produced by a compactor of a circuit-under-test in response to a test pattern;
• identifying one or more logic cones of the circuit-under-test in which a fault causing the compressed failing response might exist, the act of identifying being performed by applying a mathematical representation of the compactor to the compressed failing response;
• and
• determining a list of one or more fault candidates by simulating the test pattern being applied to the circuit-under-test in the presence of one or more simulated faults, the one or more simulated faults being located in at least one of the identified logic cones.

A method, comprising:

• receiving a list of failing test responses from a test of an electronic circuit, the responses having been compressed by a compactor, and the electronic circuit comprising scan cells that receive test responses from a plurality of respective regions of the electronic circuit;
• associating one or more of the respective regions of the electronic circuit with a selected failing test response using a description of relationships between one or more compactor inputs and one or more compactor outputs;
• finding one or more fault candidates in the one or more associated regions of the electronic circuit using a model of the electronic circuit and using a path tracing technique;
• and
• storing a list of the one or more fault candidates in one or more computer-readable memory or storage devices.

One or more computer-readable memory or storage devices storing instructions configured to cause a computer to perform a method, the method comprising:

• receiving a list of failing test responses from a test of an electronic circuit, the responses having been compressed by a compactor, and the electronic circuit comprising scan cells that receive test responses from a plurality of respective regions of the electronic circuit;
• associating one or more of the respective regions of the electronic circuit with a selected failing test response using a description of relationships between one or more compactor inputs and one or more compactor outputs;
• and
• finding one or more fault candidates in the one or more associated regions of the electronic circuit using a model of the electronic circuit and using a path tracing technique.

A system for testing a circuit-under-test, the system comprising:

• a processor;
• one or more computer-readable memory or storage instructions configured to cause the processor to perform a method, the method comprising:
• receiving a failure log comprising one or more entries indicative of failing test responses captured in the circuit-under-test and compressed by a compactor;
• for a selected entry of the failure log, identifying one or more candidate logic cones in the circuit using a transformation function indicative of which logic cones in the circuit-under-test at least partially contribute to respective failing test responses;
• and
• finding fault candidates in the one or more candidate logic cones using a representation of the circuit-under-test.