US 8,301,093 B2Granted

Receiver circuit and data transmission system

AssigneePanasonic Corporation

InventorTakefumi Yoshikawa

Life of this patent

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Abstract

A receiver circuit which can suppress a voltage amplitude appearing on a transmission line. The receiver circuit, coupled to a first and a second transmission lines which transmit information by using currents, includes a first and a second current sources, a first and a second conversion sections which convert currents which flow respectively therein to voltages, a first transistor whose source is coupled to the first current source and to the first transmission line, and whose drain is coupled to the first conversion section, and a second transistor whose source is coupled to the second current source and to the second transmission line, and whose drain is coupled to the second conversion section. The gate and the drain of the first transistor are respectively coupled to the drain and the gate of the second transistor.

Claims17

Dependent claims

A receiver circuit connectable to a first and a second transmission lines which transmit information by using currents, the receiver circuit comprising:

a first current source and a second current source;
a first conversion circuit configured to convert a current which flows the first conversion circuit to a first voltage;
a second conversion circuit configured to convert a current which flows the second conversion circuit to a second voltage;
a first transistor whose source is coupled to the first current source and connectable to the first transmission line, and whose drain is coupled to the first conversion section, the first transistor being configured to receive, at the source thereof, a current supplied from the first current source;
a second transistor whose source is coupled to the second current source and connectable to the second transmission line, and whose drain is coupled to the second conversion section, the second transistor being configured to receive, at the source thereof, a current supplied from the second current source;
a data recovery circuit configured to receive the first voltage converted by the first conversion circuit and the second voltage converted by the second conversion circuit;
and
a clock recovery circuit configured to receive the first voltage converted by the first conversion circuit and the second voltage converted by the second conversion circuit, wherein:
the gate of the first transistor is coupled to the drain of the second transistor,
the drain of the first transistor is coupled to the gate of the second transistor,
the currents which flow through the first and the second transmission lines transmit a data signal and a clock which are superimposed thereon,
a frequency of the clock is one half of a transmission frequency of the data signal,
the data recovery circuit is configured to recover the transmitted data signal according to the first and second voltages, and
the clock recovery circuit is configured to recover the transmitted clock according to the first and second voltages.

11 more elements

A data transmission system comprising:

a transmitter circuit configured to drive a first and a second transmission lines with currents;
and
a receiver circuit coupled to the first and the second transmission lines, wherein:
the transmitter circuit superimposes a data signal and a clock on the currents which flow through the first and the second transmission lines, and transmits the superimposed data signal and clock, and
the receiver circuit includes:
a first current source and a second current source;
a first conversion circuit configured to convert a current which flows the first conversion circuit to a first voltage;
a second conversion circuit configured to convert a current which flows the second conversion circuit to a second voltage;
a first transistor whose source is coupled to the first current source and to the first transmission line, and whose drain is coupled to the first conversion section, the first transistor being configured to receive, at the source thereof, a current supplied from the first current source;
a second transistor whose source is coupled to the second current source and to the second transmission line, and whose drain is coupled to the second conversion section, the second transistor being configured to receive, at the source thereof, a current supplied from the second current source;
a data recovery circuit configured to receive the first voltage converted by the first conversion circuit and the second voltage converted by the second conversion circuit;
and
a clock recovery circuit configured to receive the first voltage converted by the first conversion circuit and the second voltage converted by the second conversion circuit, wherein:
the gate of the first transistor is coupled to the drain of the second transistor,
the drain of the first transistor is coupled to the gate of the second transistor,
the data recovery circuit is configured to recover the transmitted data signal according to the first and second voltages, and
the clock recovery circuit is configured to recover the transmitted clock according to the first and second voltages.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/601,433Filed 26 Feb 2008
Priority: JP 2007-1489055 Jun 2007
Published: US 2010/0167678 A11 Jul 2010
Granted: 30 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H03K 19/018507
Using field effect transistors only: interface arrangements
H03K 3/356017
Bistable circuits: using additional transistors in the input circuit
H03K 5/06
By increasing duration; by decreasing duration: by the use of delay lines or other analogue delay elements
H03K 5/133
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: using a chain of active delay…