System for pipelined processing
AssigneeG&H Nevada-Tek
InventorsMichael L. Gough, Paul Miner
Life of this patent
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Abstract
An example embodiment includes a processor module, a pipe analyzer and a central processing unit. The processor module extracts a plurality of components from an input bit stream by extracting predetermined n-bits at a time from the input bit stream and analyzing the n-bits for components. The central processing unit has at least two pipelines for receiving the components derived from the input bit stream. The pipe analyzer is coupled between the processor module and the central processing unit for analyzing the components of the input bit stream and directing each of the components into a suitable pipeline of the central processing unit based on the analysis the pipe analyzer.
Claims7
A system for pipelined processing comprising:
- a processor module implementing a method for extracting a plurality of components from an input bit stream by extracting a predetermined n-bits at a time from the input bit stream and analyzing the n-bits for components;
- a central processing unit having at least two pipelines for receiving the components of the input bit stream for processing purposes;
- and
- a pipe analyzer coupled between the processor module and the central processing unit implementing a method for analyzing the components of the input bit stream and directing each of the components into a suitable pipeline of the central processing unit based on the analysis, the pipe analyzer utilizing a look-up table having a plurality of associated parallel processing code segments.
A computer implemented process including code segments stored in digital memory of a computer for managing input data for parallel processing comprising:
- code segments for extracting a plurality of components from an input bit stream;
- and
- code segments for analyzing the components of the input bit stream using a look-up table and assigning each component a suitable pipeline for parallel processing;
- wherein said look-up table includes a plurality of associated parallel processing code segments.
Dependencies are inferred from the claim text.