AES core with independent inputs and outputs
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
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AssigneeAltera Corporation
InventorMartin Langhammer
Estimating the term…
Encrypting data using the Advanced Encryption Standard (AES) algorithm uses pipelined registers to perform the AES processing. Any number of registers (two or more) each holds a block of plaintext data. A multiplexer accepts one block of data at a time and feeds it into the pipeline processing unit. The processing unit performs a round of encryption upon the block. A key round generator generates a set of round keys for the pipeline processing unit using a cipher key and the set of round keys are stored in parallel in memory devices, each memory device corresponding to one of the registers. The pipeline processing unit receives the correct round key for each round of encryption from the memory device corresponding to the block of data being encrypted by the add round key unit at that time. A read counter (one per register) indexes one of the round keys in the appropriate memory device thus enabling the indexed round key to be input to the pipeline processing unit for the appropriate round and block.
A hardware architecture for encrypting data using a symmetric-key encryption standard, said architecture comprising:
A method of encrypting data a symmetric-key encryption standard, said method comprising:
A hardware architecture for encrypting data using the a symmetric-key encryption standard, said architecture comprising:
Dependencies are inferred from the claim text.