Clock and data recovery with a data aligner

A system comprising:

• a first clock and data recovery (CDR) circuit configured to:
• receive a first input data stream comprising first input data bits at an input frequency, the first input data stream having been sampled from a symbol stream;
• generate a first recovered clock based on the first input data stream;
• and
• retime and demultiplex the first input data bits from the first input data stream to generate n first recovered data streams each comprising first recovered data bits at a first divided clock having a first divided clock frequency that is less than the input frequency;
• a second CDR circuit configured to:
• receive a second input data stream comprising second input data bits at the input frequency, the second input data stream having been sampled from the symbol stream;
• generate a second recovered clock based on the second input data stream;
• and
• retime and demultiplex the second input data bits from the second input stream to generate n second recovered data streams each comprising second recovered data bits at a second divided clock having a second divided clock frequency that is less than the input frequency;
• and
• a data aligner configured to:
• determine a phase difference between the first recovered clock and the second recovered clock;
• align the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams based at least in part on:
• a value of n;
• and
• the phase difference;
• combine the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams to generate one or more output data streams;
• and
• retime the first and second recovered data bits in the one or more output data streams based on either the first recovered clock or the second recovered clock.

A system comprising:

• means for:
• receiving a first input data stream comprising first input data bits at an input frequency, the first input data stream having been sampled from a symbol stream;
• generating a first recovered clock based on the first input data stream;
• and
• retiming and demultiplexing the first input data bits from the first input data stream to generate n first recovered data streams each comprising first recovered data bits at a first divided clock having a first divided clock frequency that is less than the input frequency;
• at a second CDR circuit:
• receiving a second input data stream comprising second input data bits at the input frequency, the second input data stream having been sampled from the symbol stream;
• generating a second recovered clock based on the second input data stream;
• and
• retiming and demultiplexing the second input data bits from the second input stream to generate n second recovered data streams each comprising second recovered data bits at a second divided clock having a second divided clock frequency that is less than the input frequency;
• means for determining a phase difference between the first recovered clock and the second recovered clock;
• means for aligning the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams based at least in part on:
• a value of n;
• and
• the phase difference;
• means for combining the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams to generate one or more output data streams;
• and
• means for retiming the first and second recovered data bits in the one or more output data streams based on either the first recovered clock or the second recovered clock.