Triple loop clock and data recovery (CDR)

A system comprising:

• a voltage controlled oscillator (VCO) configured to generate an output clock having an output clock frequency and an output clock phase, the output clock frequency being a function of an analog control voltage setting and a frequency gain curve, there being a plurality of frequency gain curves over a predetermined analog control voltage range that do not intersect;
• a frequency acquisition circuit configured to:
• access a reference clock having a reference clock frequency and a reference clock phase, the reference clock frequency being within a first predetermined frequency range of an input data bit frequency of an input data bit stream;
• fix the analog control voltage setting to a predetermined analog control voltage within the predetermined analog control voltage range;
• select one of the frequency gain curves within a second predetermined frequency range of the reference clock frequency at the analog control voltage setting fixed to the predetermined analog control voltage;
• adjust the analog control voltage setting from the predetermined analog control voltage to adjust the output clock frequency to be within a third predetermined frequency range of the reference clock frequency, the third predetermined frequency range being smaller than the second predetermined frequency range;
• and
• a phase-locked loop (PLL) circuit configured to:
• sample the input data bit stream;
• and
• adjust the output clock phase to be within a predetermined phase range of an input data bit phase of the input data stream.

A system comprising:

• means for accessing a reference clock having a reference clock frequency and a reference clock phase, the reference clock frequency being within a first predetermined frequency range of an input data bit frequency of an input data bit stream;
• means for generating an output clock having an output clock frequency and an output clock phase, the output clock frequency being a function of an analog control voltage setting and a frequency gain curve, there being a plurality of frequency gain curves over a predetermined analog control voltage range that do not intersect;
• means for fixing the analog control voltage setting to a predetermined analog control voltage within the predetermined analog control voltage range;
• means for selecting one of the frequency gain curves within a second predetermined frequency range of the reference clock frequency at the analog control voltage setting fixed to the predetermined analog control voltage;
• means for adjusting the analog control voltage setting from the predetermined analog control voltage to adjust the output clock frequency to be within a third predetermined frequency range of the reference clock frequency, the third predetermined frequency range being smaller than the second predetermined frequency range;
• means for sampling the input data bit stream;
• and
• means for adjusting the output clock phase to be within a predetermined phase range of an input data bit phase of the input data stream.