Information processing device, signal processing method, and signal transmission method

An information processing device, comprising:

• a first information processing module that includes
• a clock signal generating portion that generates a clock signal that is used to transmit a signal,
• an encoding portion that generates, by using the clock signal generated by the clock signal generating portion, a signal in which input data that contains first and second bit values that differ from one another is encoded such that the first bit value is expressed by a plurality of first amplitude values and the second bit value is expressed by a plurality of second amplitude values that differ from the first amplitude values, the input data also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle,
• a signal transmission portion that transmits the signal generated by the encoding portion to a second information processing module,
• a signal receiving portion that receives the signal transmitted from the second information processing module,
• a clock signal subtraction portion that subtracts, from the signal received by the signal receiving portion, the clock signal generated by the clock signal generating portion, and
• a bit value determination portion that determines third and fourth bit values that differ from one another, based on an amplitude value of the signal that has been obtained by the clock signal subtraction portion subtracting the clock signal;
• and
• the second information processing module that includes
• a signal receiving portion that receives the signal transmitted from the first information processing module,
• a clock signal extraction portion that extracts a clock signal by detecting polarity inversions in the signal received by the signal receiving portion, and
• a signal transmission portion that transmits to the first information processing module, in synchronization with the clock signal extracted by the clock signal extraction portion, a signal in which input data that contains third and fourth bit values that differ from one another is encoded such that the third bit value is expressed by a plurality of third amplitude values and the fourth bit value is expressed by a plurality of fourth amplitude values that differ from the third amplitude values, the input data also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle.

A signal processing method, comprising the steps of:

• receiving a signal in which input data that contains first and second bit values that differ from one another is encoded such that the first bit value is expressed by a plurality of first amplitude values and the second bit value is expressed by a plurality of second amplitude values that differ from the first amplitude values, the input data also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle;
• extracting a clock signal by detecting polarity inversions in the received signal;
• subtracting the extracted clock signal from the received signal;
• and
• decoding the input data by determining the first and second bit values based on the signal that has been obtained by subtracting the clock signal.

A signal transmission method, comprising the steps of:

• generating a clock signal that is used to transmit a signal, the clock signal being generated by a first information processing module;
• generating, by using the generated clock signal, a signal in which input data that contains first and second bit values that differ from one another is encoded such that the first bit value is expressed by a plurality of first amplitude values and the second bit value is expressed by a plurality of second amplitude values that differ from the first amplitude values, the input data also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle, the signal being generated by the first information processing module;
• transmitting the generated signal to a second information processing module, the signal being transmitted by the first information processing module;
• receiving the signal that has been transmitted by the first information processing module, the signal being received by the second information processing module;
• extracting the clock signal by detecting polarity inversions in the received signal, the clock signal being extracted by the second information processing module;
• transmitting to the first information processing module, in synchronization with the extracted clock signal, a signal in which input data that contains third and fourth bit values that differ from one another is encoded such that the third bit value is expressed by a plurality of third amplitude values and the fourth bit value is expressed by a plurality of fourth amplitude values that differ from the third amplitude values, the input data also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle, the signal being transmitted by the second information processing module;
• receiving the signal that has been transmitted by the second information processing module, the signal being received by the first information processing module;
• subtracting the generated clock signal from the signal that has been transmitted by the second information processing module, the clock signal being subtracted by the first information processing module;
• and
• determining the third and fourth bit values that differ from one another, based on an amplitude value of the signal that has been obtained by the first information processing module subtracting the clock signal, the third and fourth bit values being determined by the first information processing module.