Apparatus and method for dynamic scaling of ADC sampling rate to avoid receiver interference

At least one processor configured to avoid interference with a first receiver, wherein the first receiver interfaces to an analog-to-digital converter (ADC) sample clock routed between a radio frequency integrated circuit and a separate baseband integrated circuit, the at least one processor comprising:

• a first module for determining the frequency of one or more undesired signals that potentially interfere with the first receiver, wherein:
• the one or more undesired signals are generated, at least in part, by a second receiver, a co-located transmitter, or the ADC sample clock,
• the radio frequency integrated circuit comprises an ADC, and
• the ADC sample clock signal is generated on the radio frequency integrated circuit and routed to the baseband integrated circuit;
• a second module for selecting a desired sampling frequency such that at least one of the one or more potentially interfering signal components does not substantially interfere with the first receiver;
• and
• a third module for setting the sampling frequency to the desired sampling frequency.

A computer program product, comprising:

• a computer-readable medium comprising a processor interfacing to a first receiver interfacing to an analog-to-digital converter (ADC) sample clock signal routed between an RFIC and a separate baseband IC, the computer-readable medium further comprising:
• a first set of codes for causing a computer to determine the frequency of one or more undesired signals that potentially interfere with the first receiver, wherein:
• the one or more undesired signals are generated, at least in part, by a second receiver, a co-located transmitter, or the ADC sample clock signal,
• the RFIC comprises an ADC, and
• the ADC sample clock signal is generated on the RFIC and routed to the baseband IC;
• a second set of codes for causing the computer to select a desired sampling frequency such that at least one of the one or more potentially interfering signal components does not substantially interfere with the first receiver;
• and
• a third set of codes for causing the computer to set the sampling frequency to the desired sampling frequency.

An apparatus, comprising:

• a first receiver having an RFIC and a baseband IC separate from the RFIC, wherein a clock signal is routed between the RFIC and the baseband IC;
• means for determining the sampling frequency of the first receiver to avoid one or more potential interference signals occupying the desired baseband signal bandwidth of the first receiver, wherein:
• the one or more potential interference signals are generated, at least in part, by a second receiver, a co-located transmitter, or a clock signal, and
• the clock signal is generated on the RFIC and routed to the baseband IC;
• means for selecting a desired sampling frequency such that at least one of the one or more potential interference signals does not substantially interfere with the first receiver;
• and
• means for setting the sampling frequency to the desired sampling frequency.

A method for avoiding receiver interference in systems wherein an analog-to-digital converter (ADC) sample clock is routed between separate radio frequency (RF) and baseband integrated circuits (ICs), and wherein the method comprises:

• determining a frequency of one or more undesired signals that potentially interfere with a first receiver, wherein:
• the one or more undesired signals are generated, at least in part, by a second receiver, a co-located transmitter, or the ADC sample clock, and
• the RF integrated circuit comprises an ADC;
• generating an ADC sample clock signal on the RF integrated circuit;
• routing the ADC sample clock signal to the baseband IC;
• selecting a desired sampling frequency such that at least one of the one or more undesired signals does not substantially interfere with the first receiver;
• and
• setting the sampling frequency to the desired sampling frequency.