Semiconductor memory apparatus and test method thereof
AssigneeSK hynix Inc.
InventorsTae Sik Yun, Hyung Dong Lee, Jun Gi Choi, Sang Jin Byeon, Sang Hoon Shin
Life of this patent
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Abstract
A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.
Claims41
A semiconductor memory apparatus comprising:
- a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a predetermined clock cycle than the first clock;
- and
- an address/command input clock generation unit configured to output one of the first clock and the second clock as an address/command input clock according to the enable signal.
A semiconductor memory apparatus comprising:
- a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer to a target clock cycle than the first clock;
- and
- a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal.
A semiconductor memory apparatus comprising:
- a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a predetermined clock cycle than the first clock;
- a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal;
- and
- an address/command input clock generation unit configured to output one of the first clock and the second clock as an address/command input clock according to the enable signal.
A semiconductor memory apparatus comprising:
- a clock control unit configured to receive a first clock and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock;
- a DLL input clock generation unit configured to output the first clock as a DLL input clock;
- an address/command input clock generation unit configured to output the second clock as an address/command input clock;
- and
- a burst length exchanger configured to change sequence of burst length signals.
A method for testing a semiconductor memory apparatus, comprising the steps of:
- is receiving a first clock and generating a second clock which has a cycle closer in length to a predetermined clock cycle than the first clock;
- and
- outputting the second clock as a DLL input clock and an address/command input clock.
A method for testing a semiconductor memory apparatus, comprising the steps of:
- receiving a first clock and generating a second clock which has a cycle closer in length to a predetermined clock cycle than the first clock;
- and
- outputting the second clock as an address/command input clock and the first clock as a DLL input clock.
Dependencies are inferred from the claim text.