Data transfer circuit and semiconductor memory device including the same
AssigneeHynix Semiconductor Inc.
InventorJi-Hyae Bae
Life of this patent
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Abstract
A data transfer circuit has a reduced number of lines for transferring a training pattern used in a read training for high speed operation, by removing a register for temporarily storing the training pattern, and a semiconductor memory device including the data transfer circuit. The data transfer circuit includes a latch unit and a buffer unit. The latch unit latches one bit of a training pattern data input together with a training pattern load command whenever the training pattern load command is input. The buffer unit loads a plurality of bits latched in the latch unit, including the one bit of training pattern data, in response to a strobe signal.
Claims21
A data transfer circuit, comprising:
- a latch unit configured to latch one bit of a training pattern data input together with a training pattern load command whenever the training pattern load command is input;
- and
- a buffer unit configured to load a plurality of bits latched in the latch unit, including the one bit of training pattern data, in response to a strobe signal.
A semiconductor memory device, comprising:
- a data transfer circuit having a buffer unit configured to latch one bit of a training pattern data whenever a training pattern load command is input, in response to location signals, and configured to load a plurality of bits, including the one bit of latched training pattern data, on the buffer unit in response to a strobe signal;
- a decoding circuit configured to generate location signals each indicating a location in the buffer unit, into which the training pattern data are loaded, according to a control signal, wherein the training pattern data and the control signal are input together with the training pattern load command;
- and
- a strobe signal generation circuit configured to generate a strobe signal according to the control signal.
Dependencies are inferred from the claim text.