Apparatus and method for transmitting/receiving signals at high speed
AssigneeHynix Semiconductor Inc.
InventorsChang-Ho Do, Jae-Il Kim
Life of this patent
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Abstract
A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.
Claims14
A semiconductor integrated circuit, comprising:
- a driver configured to apply data to a data line in response to a control signal;
- a data line controller configured to control a voltage level of the data line according to whether or not the voltage level of the data line is greater than a logic threshold voltage prior to activation of the control signal;
- and
- a pre-controller configured to output a pre-control signal for controlling the data line controller in response to the control signal and a delayed enable signal, wherein the control signal is generated by delaying an enable signal corresponding to an external read command by a first delay time and the delayed enable signal is generated by delaying the enable signal by a second delay time shorter than the first delay time.
A method for driving a semiconductor integrated circuit, the method comprising:
- applying data to a data line in response to a control signal;
- controlling a voltage level of the data line according to whether or not the voltage level of the data line is greater than a logic threshold voltage prior to activation of the control signal;
- and
- outputting a pre-control signal for controlling the controlling operation of the voltage level of the data line in response to the control signal and a delayed enable signal, wherein the control signal is generated by delaying an enable signal corresponding to an external read command by a first delay time and the delayed enable signal is generated by delaying the enable signal by a second delay time shorter than the first delay time.
Dependencies are inferred from the claim text.