Piecewise erasure of flash memory

A system, comprising:

• a first circuit to generate and to provide multiple piecewise-erase commands associated with a given storage cell in a second circuit external to the first circuit;
• a link coupled to the first circuit;
• and
• the second circuit coupled to the link, wherein the second circuit includes:
• a memory including multiple storage cells;
• an interface, which is coupled to the link, to receive the multiple piecewise-erase commands;
• control logic, coupled to the interface and the memory, to execute the multiple piecewise-erase commands, wherein execution of the multiple piecewise-erase commands is sufficient to erase information stored in the given storage cell while execution of a single piecewise-erase command is insufficient to erase the information stored in the given storage cell;
• and
• a feedback circuit, coupled to the memory and the control logic, to monitor an erase state of the given storage cell and to generate an indication in response to the information stored in the given storage cell having been erased.

A method for executing multiple piecewise-erase commands, comprising:

• receiving the multiple piecewise-erase commands associated with a given storage cell in a memory in a circuit, wherein the multiple piecewise-erase commands are received from another circuit external to the circuit;
• executing the multiple piecewise-erase commands, wherein execution of the multiple piecewise-erase commands is sufficient to erase information stored in the given storage cell while execution of a single piecewise-erase command is insufficient to erase the information stored in the given storage cell;
• monitoring an erase state of the given storage cell using a feedback circuit;
• and
• generating an indication in response to the information stored in the given storage cell having been erased.

A circuit, comprising:

• control logic to select an operation mode of the circuit, wherein in a first operation mode the control logic is to generate a single erase command that, when executed by another circuit external to the circuit, is sufficient to erase information stored in a given storage cell in a memory included in the other circuit;
• and wherein in a second operation mode the control logic generates multiple piecewise-erase commands that, when executed by the other circuit, are sufficient to erase the information stored in the given storage cell, while a single piecewise-erase command, when executed by the other circuit, is insufficient to erase the information stored in the given storage cell;
• and
• an interface, coupled to the control logic and which is to couple to a link, to receive the single erase command from the control logic in the first operation mode or the multiple piecewise-erase commands from the control logic in the second operation mode, and to transmit the single erase command or the multiple piecewise-erase commands to the other circuit via the link.