Cost saving electrically-erasable-programmable read-only memory (EEPROM) array

A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, comprising:

• a plurality of parallel bit lines, that are classified into a plurality groups of bit lines, containing a first group bit lines;
• a plurality of parallel word lines, arranged perpendicular to said bit lines, and containing a first word line and a second word line;
• a plurality of parallel common source lines, arranged parallel to said word line, containing a first common source line;
• and
• a plurality of sub-memory arrays, each is connected to a group of said bit lines, two said word lines, and a said common source line, each of said sub-memory arrays includes:
• a first memory cell, connected to said first group bit lines, said first common source line, and said first word line, and
• a second memory cell, connected to said first group bit lines, said first common source line, and said second word line, said first memory cell and said second memory cell are arranged opposite to each other, and are located on two different sides of the first common source line;
• wherein said first group bit line includes said bit line, connected to said first and second memory cells and
• when said first and said second memory cells both contain a P-type field effect transistor located in an N-type well region or an N-type substrate, said first and second memory cells are both said operation memory cells, in selecting one of said operation memory cells as said selected memory cell in carrying out operations, said operation memory cells, that are connected to said same bit line connecting to said selected memory cell, but not connected to said same common source line connecting to said selected memory cell, are referred to as said plurality of common bit memory cells;
• said operation memory cell, that is connected to said same bit line and said same common source line, both connecting to said selected memory cell, is referred to as said common source memory cell;
• and said operation memory cells, that are connected to said same word line connecting to said selected memory cell, are referred to as said plurality of common word memory cells;
• and rest of said operation memory cells are referred to said plurality of unselected memory cells,
• when operating on said selected memory cells, performing the following voltage applications as required:
• applying said substrate voltage Vsubn on said N-type well region or said N-type substrate connecting to said selected memory cell;
• applying said first bit voltage Vb1, said first word voltage Vw1, said first common source voltage Vs1 on said bit line, said word line, and said common source line, all connecting to said selected memory cell;
• applying said second word voltage Vw2, said second common source voltage Vs2 respectively on said word line and said common source line, both connecting to each said common bit memory cell;
• applying said second bit voltage Vb2, said first common source voltage Vs1 on said bit line and said common source line, both connecting to each said common word memory cell;
• applying said second word voltage Vw2 on said word line connecting to said common source memory cell;
• and applying said second bit voltage Vb2, said second word voltage Vw2, and said second common source voltage Vs2 on said bit line, said word line, and said common source line, all connecting to each said unselected memory cell, such that,
• when writing data into a memory, the following conditions are to be satisfied:
• Vb2 is floating, Vsubn>Vs1>Vb1, Vsubn>Vs1>Vw1, Vsubn>Vs2>Vb1, and Vsubn>Vw2>Vb1;
• and
• when erasing data from the memory, the following conditions are to be satisfied:
• Vb2 is floating, Vsubn=Vs1≧Vw1>Vb1, Vsubn>Vs2>Vb1, and Vsubn>Vw2>Vb1.

A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, comprising:

• a plurality of parallel bit lines, that are classified into a plurality groups of bit lines, containing a first group bit lines;
• a plurality of parallel word lines, arranged perpendicular to said bit lines, and containing a first word line and a second word line;
• a plurality of parallel common source lines, arranged parallel to said word line, containing a first common source line;
• and
• a plurality of sub-memory arrays, each is connected to a group of said bit lines, two said word lines, and a said common source line, each of said sub-memory arrays includes:
• a first memory cell, connected to said first group bit lines, said first common source line, and said first word line, and
• a second memory cell, connected to said first group bit lines, said first common source line, and said second word line, said first memory cell and said second memory cell are arranged opposite to each other, and are located on two different sides of the first common source line;
• wherein said first memory cell further comprises:
• said field effect transistor, having a floating gate, and with its drain connected to said first group bit lines, and with its source connected to said first common source line;
• and
• a capacitor, with its one end connected to said floating gate, and with its other end connected to said first word line, so as to receive voltage of said first word line, said field effect transistor receives voltage of said first common source line, and voltage of said first group bit lines, such that said field effect transistor writes data into said floating gate, or erases data from said floating gate.

A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, comprising:

• a plurality of parallel bit lines, that are classified into a plurality groups of bit lines, containing a first group bit lines;
• a plurality of parallel word lines, arranged perpendicular to said bit lines, and containing a first word line and a second word line;
• a plurality of parallel common source lines, arranged parallel to said word line, containing a first common source line;
• and
• a plurality of sub-memory arrays, each is connected to a group of said bit lines, two said word lines, and a said common source line, each of said sub-memory arrays includes:
• a first memory cell, connected to said first group bit lines, said first common source line, and said first word line, and
• a second memory cell, connected to said first group bit lines, said first common source line, and said second word line, said first memory cell and said second memory cell are arranged opposite to each other, and are located on two different sides of the first common source line;
• wherein said second memory cell further comprises:
• said field effect transistor, having a floating gate, and with its drain connected to said first group bit lines, and with its source connected to said first common source line;
• and
• a capacitor, with its one end connected to said floating gate, and with its other end connected to said second word line, so as to receive voltage of said second word line, said field effect transistor receives voltage of said first common source line, and voltage of said first group bit lines, such that said field effect transistor writes data into said floating gate, or erases data from said floating gate.