Flash memory program inhibit scheme

A NAND flash device comprising:

• row circuitry for driving word lines with voltages between VSS and a programming voltage level;
• bitline circuits for biasing bit lines to one of a program inhibit voltage and a program enable voltage;
• a memory array having NAND strings connected to bit lines and source lines, and having memory cells connected to the word lines, each NAND string inhibited from programming being coupled to a bitline set to the program inhibit voltage for precharging memory cell channels when all word lines of the NAND string are driven to at least a first voltage level, and the NAND strings including
• a selected memory cell having a selected word line increased to a programming voltage level;
• an upper memory cell adjacent the selected memory cell and having an upper selected word line reduced to a second voltage level higher than VSS while the selected word line is at the programming voltage level;
• and,
• a lower memory cell adjacent the selected memory cell and having a lower selected word line reduced to a third voltage level while the selected word line is at the programming voltage level.