NAND flash memory
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Maejima, Katsuaki Isobe
Life of this patent
Estimating the term…
Abstract
A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
Claims10
A NAND flash memory in which all bit lines are pre-charged and simultaneously read, comprising:
- a memory cell array including a plurality of blocks each of which includes
- a memory cell unit, which includes a plurality of memory cells connected in series to each other each of which is formed in a p-type well surrounded by a n-type well formed in a p-type semiconductor substrate,
- a drain-side select gate transistor that is connected to a drain-side select gate line at the gate thereof and connects the memory cell unit to a bit line, and
- a source-side select gate transistor that is connected to a source-side select gate line at the gate thereof and connects the memory cell unit to a source line;
- a row decoder selecting word lines, and selecting the blocks by controlling the voltage applied to the drain-side select gate line and the source-side select gate line;
- and
- a sense amplifier applying a voltage to bit lines of the memory cell array,
- wherein in a read operation:
- the p-type semiconductor substrate is set at a ground potential,
- a start time of charging the bit line to a first voltage, a start time of charging the source line, the n-type well and the p-type well to a second voltage, and a start time of charging the drain-side select gate line and the source-side select gate line in the block not selected to a third voltage are equal, and
- the second voltage is between the ground potential and the first voltage, and the third voltage is higher than the ground potential and is equal to or lower than the second voltage.
A NAND flash memory in which all bit lines are pre-charged and simultaneously read, comprising:
- a memory cell array including a plurality of blocks each of which includes
- a memory cell unit, which includes a plurality of memory cells connected in series to each other each of which is formed in a p-type well surrounded by a n-type well formed in a p-type semiconductor substrate,
- a drain-side select gate transistor that is connected to a drain-side select gate line at the gate thereof and connects the memory cell unit to a bit line, and
- a source-side select gate transistor that is connected to a source-side select gate line at the gate thereof and connects the memory cell unit to a source line;
- a row decoder selecting word lines, and selecting the blocks by controlling the voltage applied to the drain-side select gate line and the source-side select gate line;
- and
- a sense amplifier applying a voltage to bit lines of the memory cell array,
- wherein, in a verifying operation:
- the p-type semiconductor substrate is set at a ground potential,
- a start time of charging the bit line to a first voltage, a start time of charging the source line, the n-type well and the p-type well to a second voltage, and a start time of charging the drain-side select gate line and the source-side select gate line in the block not selected to a third voltage are equal, and
- the second voltage is between the ground potential and the first voltage, and the third voltage is higher than the ground potential and is equal to or-lower than the second voltage.
Dependencies are inferred from the claim text.