Semiconductor and flash memory systems

A flash memory system, comprising:

• a flash memory device which stores page data in a plurality of page data cells of a first non-volatile memory and spare data in a plurality of spare data cells of a second non-volatile memory, reads the stored page data and the stored spare data when a read command is applied from an external portion, and sequentially selects a plurality of first or second page buffers according to address information applied from the external portion to output the page data and the spare data;
• a memory controller which provides address information and a command to the flash memory device and controls an operation of the flash memory device;
• and
• a memory bus which serves as a medium for transmitting data, address information and a command between the flash memory device and the memory controller;
• wherein the first non-volatile memory and the second non-volatile memory are different types of non-volatile memory,
• wherein the flash memory device comprises:
• a latching and decoding portion for receiving address information and a command from an external portion, and latching and decoding the address information and the command,
• the first non-volatile memory including the plurality of page data cells and the plurality of first page buffers, storing page data in the plurality of page data cells, and sequentially selecting the plurality of first page buffers according to the address information to output data when a read command is applied from the external portion;
• the second non-volatile memory including the plurality of spare data cells respectively adjacent the plurality of page data cells and the plurality of second page buffers, storing the spare data in the plurality of spare data cells, scanning the spare data to temporarily corresponding information when a file system is mounted, and sequentially selecting the plurality of second page buffers to output data according to the address information when the read command is applied;
• and
• a control logic which controls operations of the first and second non-volatile memories in response to the decoded address information and the decoded command, and
• wherein the control logic controls a wear leveling function and a garbage collecting function which are necessary during a write operation of the first non-volatile memory and controls the number of erase times of the first non-volatile memory cell and a block setting of the first non-volatile memory to be deleted.