Method and circuit for calibrating data capture in a memory controller

In a data processing system having a memory controller for controlling access to a memory, a method for calibrating a gating signal with data read from the memory, the gating signal for aligning the data to a clock signal, the method comprising:

• entering a gating signal calibration mode;
• writing a first calibration data pattern to the memory, the first calibration data pattern having a first portion and a second portion;
• writing a second calibration data pattern to a register in the memory controller, the second calibration data pattern being equal to the first portion of the first calibration data pattern, and the second calibration pattern not being equal to the second portion of the first calibration data pattern;
• setting a time delay of the gating signal to a first value;
• reading the first calibration data pattern from the memory to the memory controller;
• comparing the first calibration data pattern to the second calibration data pattern bit-by-bit in response to the gating signal;
• detecting if a transition from the first portion of the first calibration data pattern to the second portion of the first calibration data pattern occurs within a time period;
• and
• if the transition does not occur within the time period, adjusting the time delay of the gating signal by a second value.

A memory controller comprising:

• a logic circuit having a first input for receiving a clock signal, a second input coupled to a reference voltage, a control input for receiving a gating signal, and an output;
• a first-in, first-out memory (FIFO) having a clock input coupled to the output of the logic circuit, a data input coupled to receive data from a memory, and an output;
• a comparator having a first input coupled to a the output of the FIFO, a second input coupled to receive a calibration pattern, the calibration pattern predetermined to match with a first portion of data from the FIFO, and the calibration pattern predetermined to not match with a second portion of data from the FIFO;
• and
• a detection and adjustment circuit for detecting if a transition from the first portion of the data to the second portion of the data occurs within a predetermined time period, and in response to detecting that the transition does not occur within the predetermined time period, causing a timing of the gating signal to be adjusted.